17672382. TRENCH-TYPE BEOL MEMORY CELL simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
Contents
TRENCH-TYPE BEOL MEMORY CELL
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Tzu-Yu Chen of Kaohsiung City (TW)
Sheng-Hung Shih of Hsinchu City (TW)
TRENCH-TYPE BEOL MEMORY CELL - A simplified explanation of the abstract
This abstract first appeared for US patent application 17672382 titled 'TRENCH-TYPE BEOL MEMORY CELL
Simplified Explanation
The abstract describes a patent application for an integrated chip that includes a memory cell within a metal interconnect. The memory cell is formed over openings in a dielectric structure and may be an FeRAM memory cell. The layers of the memory cell line the openings, with a lower electrode layer, a data storage layer, and an upper electrode descending into the openings. The lower electrode layer may pass through an etch stop layer and contact a lower interconnect. There may also be multiple top electrode vias, offset from the opening, providing a large area and low threshold voltages.
- Integrated chip with a memory cell within a metal interconnect
- Memory cell may be an FeRAM memory cell
- Memory cell is formed over openings in a dielectric structure
- Layers of the memory cell line the openings
- Lower electrode layer, data storage layer, and upper electrode descend into the openings
- Lower electrode layer passes through an etch stop layer and contacts a lower interconnect
- Multiple top electrode vias offset from the opening
- Provides a large area, leading to low threshold voltages
Potential Applications
- Memory storage in integrated circuits
- FeRAM memory cells for non-volatile data storage
Problems Solved
- Provides a memory cell structure within a metal interconnect, saving space and improving integration
- Large area of the memory cell structure leads to low threshold voltages
Benefits
- Increased memory storage capacity in integrated circuits
- Improved integration of memory cells within the chip design
- Lower threshold voltages for improved performance and energy efficiency
Original Abstract Submitted
An integrated chip includes a memory cell within a BEOL metal interconnect. The memory cell may be an FeRAM memory cell. The memory cell is formed over a plurality of openings in a dielectric structure that includes an inter-level dielectric layer. The openings may be form an array or another two-dimensional pattern. The layers of the memory cell line the openings whereby each of a lower electrode layer, a data storage layer, and an upper electrode descend into the openings. The lower electrode layer may pass through an etch stop layer and contact a lower interconnect. There may be a plurality of top electrode vias. The top electrode vias may be offset from the opening. This memory cell structure provides a large area, which leads to low threshold voltages.
