17461952. SEMICONDUCTOR DIE simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

SEMICONDUCTOR DIE

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Yen-Kun Lai of New Taipei City (TW)

Chien-Hao Hsu of Hsinchu County (TW)

Wei-Hsiang Tu of Hsinchu City (TW)

Kuo-Chin Chang of Chiayi City (TW)

Mirng-Ji Lii of Hsinchu County (TW)

SEMICONDUCTOR DIE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17461952 titled 'SEMICONDUCTOR DIE

Simplified Explanation

The abstract describes a semiconductor die that includes a semiconductor substrate, an interconnect structure, and a conductive bump. The interconnect structure is made up of stacked interconnect layers, each consisting of a dielectric layer and an interconnect wiring embedded in it. The interconnect wiring of the first layer includes a first via and second vias, all located at the same level height. The conductive bump is placed on the interconnect structure, with a base portion between the protruding portion and the first via.

• The semiconductor die includes a semiconductor substrate, interconnect structure, and conductive bump.
• The interconnect structure consists of stacked interconnect layers with dielectric layers and embedded interconnect wiring.
• The first interconnect layer has a first via and second vias, all at the same level height.
• The conductive bump has a base portion and a protruding portion connected to it, with the base portion between the protruding portion and the first via.

Potential Applications

• Integrated circuits
• Semiconductor devices
• Electronic components

Problems Solved

• Efficient electrical connection between semiconductor substrate and conductive bump
• Improved interconnect structure for stacked interconnect layers

Benefits

• Enhanced performance and reliability of semiconductor die
• Simplified manufacturing process
• Higher density of interconnects

Original Abstract Submitted

A semiconductor die includes a semiconductor substrate, an interconnect structure, and a conductive bump. The interconnect structure is disposed on and electrically connected to the semiconductor substrate. The interconnect structure includes stacked interconnect layers. Each of the stacked interconnect layers includes a dielectric layer and an interconnect wiring embedded in the dielectric layer. The interconnect wiring of a first interconnect layer among the stacked interconnect layers further includes a first via and second vias. The first via electrically connected to the interconnect wiring. The second vias connected to the interconnect wiring, and the first via and the second vias are located on a same level height. The conductive bump is disposed on the interconnect structure. The conductive bump includes a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via.