US Patent Application 18360265. INTEGRATED CIRCUITS WITH BACKSIDE POWER RAILS simplified abstract
Contents
INTEGRATED CIRCUITS WITH BACKSIDE POWER RAILS
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Chih-Chao Chou of Hsinchu (TW)
Kuo-Cheng Chiang of Hsinchu County (TW)
Shi Ning Ju of Hsinchu City (TW)
Wen-Ting Lan of Hsinchu City (TW)
Chih-Hao Wang of Hsinchu County (TW)
INTEGRATED CIRCUITS WITH BACKSIDE POWER RAILS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18360265 titled 'INTEGRATED CIRCUITS WITH BACKSIDE POWER RAILS
Simplified Explanation
The patent application describes a method for manufacturing semiconductor devices.
- The method involves receiving a substrate with multiple semiconductor layers.
- Fins are formed over one of the semiconductor layers, and a trench is created between two of the fins.
- A dummy material is deposited in the trench, and a gate structure is formed over the fins.
- Source/drain features are formed over the fins, and the substrate is bonded to a carrier wafer.
- The first and second semiconductor layers are removed to expose the dummy material, which is then removed from the trench.
- A conductive material is deposited in the trench, and the substrate is bonded to a silicon substrate.
- The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.
Original Abstract Submitted
Semiconductor devices and methods are provided. A method according to the present disclosure includes receiving a substrate that includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; forming a plurality of fins over the third semiconductor layer; forming a trench between two of the plurality of fins; depositing a dummy material in the trench; forming a gate structure over channel regions of the plurality of the fins; forming source/drain features over source/drain regions of the plurality of the fins; bonding the substrate on a carrier wafer; removing the first and second semiconductor layers to expose the dummy material; removing the dummy material in the trench; depositing a conductive material in the trench; and bonding the substrate to a silicon substrate such that the conductive material is in contact with the silicon substrate. The trench extends through the third semiconductor layer and has a bottom surface on the second semiconductor layer.