Tesla, Inc. patent applications on September 5th, 2024
Patent Applications by Tesla, Inc. on September 5th, 2024
Tesla, Inc.: 2 patent applications
Tesla, Inc. has applied for patents in the areas of B60G17/018 (1), B60G17/04 (1), G01C21/00 (1), G01C21/34 (1), G06N3/08 (1) B60G17/018 (1), G06N3/08 (1)
With keywords such as: road, network, processing, roughness, used, architecture, bits, reduce, vehicle, and suspension in patent application abstracts.
Patent Applications by Tesla, Inc.
20240294048. VEHICLE SUSPENSION CONTROL SYSTEM_simplified_abstract_(tesla, inc.)
Inventor(s): Blane Frye of San Francisco CA (US) for tesla, inc., Soroush MohammadJafaryvahed of Santa Clara CA (US) for tesla, inc., Aleksei Potov of Los Gatos CA (US) for tesla, inc., Julian Pitt of East Palo Alto CA (US) for tesla, inc., Harris Yong of Sunnyvale CA (US) for tesla, inc., Oruganti Prashanth Sharma of Campbell CA (US) for tesla, inc.
IPC Code(s): B60G17/018, B60G17/04, G01C21/00, G01C21/34
CPC Code(s): B60G17/018
Abstract: systems and methods for vehicle suspension control. an example method includes obtaining a road roughness map associated with a geographic area in which the vehicle is located, the road roughness map reflecting road condition metrics for road segments that form roads included in the geographic area. based on the road roughness map, it is determined that a threshold percentage of road segments along an upcoming threshold distance of a navigable route exceed a threshold road condition metric. suspension of the vehicle is adjusted, with the suspension being adjusted to reduce the effects of road roughness.
20240296330. NEURAL NETWORKS FOR EMBEDDED DEVICES_simplified_abstract_(tesla, inc.)
Inventor(s): Forrest Nelson Iandola of San Jose CA (US) for tesla, inc., Harsimran Singh Sidhu of Fremont CA (US) for tesla, inc., Yiqi Hou of Berkeley CA (US) for tesla, inc.
IPC Code(s): G06N3/08, G06F7/575
CPC Code(s): G06N3/08
Abstract: a neural network architecture is used that reduces the processing load of implementing the neural network. this network architecture may thus be used for reduced-bit processing devices. the architecture may limit the number of bits used for processing and reduce processing to prevent data overflow at individual calculations of the neural network. to implement this architecture, the number of bits used to represent inputs at levels of the network and the related filter masks may also be modified to ensure the number of bits of the output does not overflow the resulting capacity of the reduced-bit processor. to additionally reduce the load for such a network, the network may implement a “starconv” structure that permits the incorporation of nearby nodes in a layer to balance processing requirements and permit the network to learn from context of other nodes.
