Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on August 1st, 2024
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd. on August 1st, 2024
Taiwan Semiconductor Manufacturing Company, Ltd.: 76 patent applications
Taiwan Semiconductor Manufacturing Company, Ltd. has applied for patents in the areas of H01L29/66 (17), H01L23/00 (12), H01L29/06 (11), H01L29/423 (10), H01L21/02 (9) H01L25/16 (2), H01L27/0924 (2), H01L27/0922 (2), H01L27/0886 (2), G11C13/0069 (2)
With keywords such as: layer, structure, semiconductor, gate, region, conductive, memory, substrate, dielectric, and device in patent application abstracts.
Patent Applications by Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s): Shao-Chien Chiu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Chun Peng of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., To-Yu Chen of Yunlin (TW) for taiwan semiconductor manufacturing company, ltd., Mao-Chih Huang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01N21/88, H01L21/66
CPC Code(s): G01N21/88
Abstract: a defect inspection method is disclosed. the method includes acquiring a plurality of first images of a first specimen in a first resolution. the method includes acquiring a plurality of second images of the first specimen in a second resolution, the second resolution being different from the first resolution. the method includes training a machine learning model with a training set, wherein the training set comprises at least the plurality of first images of the first specimen and the plurality of second images of the first specimen. the method includes acquiring a third image of a second specimen in the first resolution. the method includes inputting the third image into the trained machine learning model. the method includes generating, based on the trained machine learning model, a fourth image of the second specimen in the second resolution.
Inventor(s): Hsiang-Hui CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Jung CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R31/28, H01L27/02
CPC Code(s): G01R31/2879
Abstract: a voltage tracking circuit includes a first, second, third and fourth transistor. the first transistor is in a first well, the first transistor including a first source terminal and a first body terminal that are coupled to a first voltage supply. the second transistor includes a second source terminal being coupled to the first drain terminal, a second gate terminal being coupled to a pad voltage terminal and configured to receive a pad voltage. the third transistor is in a second well, and includes a third gate terminal coupled to the first voltage supply, and a third body terminal coupled to a first node. the fourth transistor includes a fourth drain terminal coupled to the third source terminal, a fourth gate terminal coupled to the third gate terminal and the first voltage supply, and a fourth source terminal coupled to the pad voltage terminal.
Inventor(s): Huan-Neng CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Lin LIU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei HSU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jo-Yu WU of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., CHANG-FEN HU of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Yu LI of Hsinchu city (TW) for taiwan semiconductor manufacturing company, ltd., Bo-Ting CHEN of Fengyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05F1/595, G05F1/575, H03K19/0175
CPC Code(s): G05F1/595
Abstract: a circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. the current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
Inventor(s): Jaspal Singh Shah of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Atul Katoch of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F1/10, G06F1/12
CPC Code(s): G06F1/10
Abstract: circuits and methods are provided for a clock generation circuit that includes a first transistor, wherein a gate of the first transistor is connected to a clock signal, a second transistor, connected in parallel to the first transistor, and a driving circuit, coupled to the second transistor, and comprising an input and an output, wherein the input of the driving circuit is connected to the clock signal, the output of the driving circuit is connected to a gate of the second transistor, and the driving circuit is configured to reduce a slew of the clock signal.
Inventor(s): Cheng-Hsiang Hsieh of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Min-Shueh Yuan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Mu-Shan Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., You-Cheng Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F1/12, G06F1/10
CPC Code(s): G06F1/12
Abstract: a semiconductor package includes a plurality of semiconductor chips. the semiconductor package includes a redistribution structure. the redistribution structure can be configured to electrically couple the plurality of semiconductor chips to each other, and further configured to transmit a single global clock signal. data transferred across the plurality of semiconductor chips can be synchronized in a clock domain to which the single global clock signal belongs.
Inventor(s): Shih-Lien Linus Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F12/0804, G06F12/06, G11C11/4093, G11C11/4096
CPC Code(s): G06F12/0804
Abstract: a memory device is described, including a command decoder configured to receive a copy command to copy data stored in a first memory location to a second memory location without transmitting the data to an external controller, a memory array electrically connected to the command decoder and including a plurality of memory locations including the first memory location and the second memory location, a data line electrically connected to the memory array and configured to receive, from the first memory location, the data to be transmitted to the second memory location through the same data line, and an output buffer configured to store the data received from the first memory location through the data line to be written into the second memory location without transmitting the data to the external controller.
Inventor(s): Chih-Cheng CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Zhong ZHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hsiang MA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/394, H03K3/356
CPC Code(s): G06F30/392
Abstract: a semiconductor device includes: single-bit flip-flop regions (sbff regions) which comprise a multi-bit flip-flop (mbff) region; the mbff region having a two-dimensional floor plan represented by a grid including rows and a first column extending in corresponding first and perpendicular second directions, each sbff region representing an intersection of a corresponding row and column; the sbff regions being coupled in a daisy chain for which an output of a preceding one of the sbff regions in the daisy chain is coupled to an input of a succeeding one of the sbff regions in the daisy chain; and orientations of the sbff regions relative to the first direction (�-orientations) being arranged in an alternating pattern relative to the second direction so that a two-dimensional representation of a flow path of a data signal along the first column has a serpentine shape.
Inventor(s): Nien-Yu TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Chang HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ju YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Hsin Sean LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, G06F30/39, G06F30/398, G06F119/18, H01L27/02
CPC Code(s): G06F30/392
Abstract: a semiconductor device includes a first cell. the first cell includes a first functional feature, a first sensitivity region, at least one anchor node, wherein each of the at least one anchor node is different from the first functional feature, and a number of anchor nodes of the at least one anchor node linked to the first functional feature is based on a position of the first functional feature relative to the first sensitivity region. the semiconductor device further includes a second cell abutting the first cell. the second cell includes a second functional feature, wherein the second functional feature satisfies a minimum spacing requirement with respect to the first functional feature.
Inventor(s): Hung-Chih OU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hao CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/398, G06F30/30, G06F119/06, G06F119/12
CPC Code(s): G06F30/398
Abstract: a semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.
Inventor(s): Yen Lin CHUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kao-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei Min CHAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C5/06, H01L23/522, H01L23/528, H10B10/00
CPC Code(s): G11C5/063
Abstract: a memory cell includes a first, second, third, and fourth transistor, a first and a second inverter, and a first and second word line. the first inverter is coupled to the first and third transistor. the second inverter is coupled to the first inverter and the first and third transistor. the first word line is configured to supply a first word line signal, is on a first metal layer above a front-side of a substrate, and is coupled to the first and third transistor. the second word line is configured to supply a second word line signal, and is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate, and is coupled to the second and fourth transistor. at least the first, second, third or fourth transistor are on the front-side of the substrate.
Inventor(s): Katherine Chiang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Min Cao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yuh-Jier Mii of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih Lai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/16, H10B61/00, H10N50/01, H10N50/80, H10N50/85
CPC Code(s): G11C11/1659
Abstract: in some embodiments, the present disclosure relates to an integrated chip. the integrated chip includes an operative memory device. a regulating access apparatus is coupled to the operative memory device. the regulating access apparatus includes one or more regulating mtj devices respectively having a regulating free layer, a regulating dielectric barrier layer, and a regulating pinned layer separated from the regulating free layer by the regulating dielectric barrier layer. the regulating pinned layer continuously extends between opposing outermost sidewalls of the regulating dielectric barrier layer.
Inventor(s): Hidehiro FUJIWARA of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Haruki MORI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chang ZHAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/417, G06F7/544, G11C11/412
CPC Code(s): G11C11/417
Abstract: a memory device includes a memory array of a plurality of memory cells, and first and second multiply accumulate (mac) circuits. the memory cells include first and second memory cell groups. the first memory cell group includes first rows of memory cells coupled to first bit lines. the second memory cell group includes second rows of memory cells coupled to second bit lines. the first rows of memory cells and the second rows of memory cells are alternately arranged along a column direction of the first bit lines and the second bit lines. the first bit lines and the second bit lines are alternately arranged along a row direction of the first rows and the second rows. the first and second mac circuits are correspondingly coupled, correspondingly through the first and second bit lines, to the memory cells of the first and second memory cell groups.
Inventor(s): Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Chieh Liu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Jen Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Fan Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jer-FU Wang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Iuliana Radu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419, G11C11/412, H01L23/528, H10B10/00
CPC Code(s): G11C11/419
Abstract: a semiconductor device includes a memory cell including a first transistor, a second transistor, and a third transistor. the first transistor has a first gate terminal and the second transistor has a second gate terminal, the first gate terminal and the second gate terminal being connected to a first word line and a second word line, respectively. the first transistor has a pair of first source/drain terminals and the second transistor has a pair of second source/drain terminals, one of the pair of first source/drain terminals and one of the pair of second source/drain terminals being connected to a common bit line. the third transistor has a third gate terminal connected to the other of the pair of first source/drain terminals, and a pair of third source/drain terminals connected to the other of the pair of second source/drain terminals and a supply voltage, respectively.
Inventor(s): Wei-Xiang YOU of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Yuan CHEN of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Yin WANG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Szuya LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/419, G11C11/412, H01L23/528, H10B10/00
CPC Code(s): G11C11/419
Abstract: embodiments of the present disclosure relate to a sram (static random access memory) bit cell. more particularly, embodiments of the present disclosure relate to a single port, 8t sram cell with write enhance pass gate transistors. particularly, two write enhance pass gate transistors are parallelly connected with the pass gate transistors in a standard 6t sram cell. the write enhance pass gate transistors are independently controlled from the pass gate transistor using a write enhance word line. in some embodiments, the single port, 8t sram cell according to the present disclosure may be implemented by stacked complementary fets. empty or dummy pmos transistors in a standard 6t stacked cfet sram cell are used as pass gate transistors or write enhance pass gate transistors.
Inventor(s): Zheng-Jun Lin of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Cheng Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Der Chih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Ling Tseng of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C13/00
CPC Code(s): G11C13/0064
Abstract: the disclosed invention presents a self-tracking reference circuit that compensates for ir drops and achieves the target resistance state at different temperatures after write operations. the disclosed self-tracking reference circuit includes a replica access path, a configurable resistor network, a replica selector mini-array and a step current generator that track pvt variations to provide a pvt tracking level for rram verify operation.
Inventor(s): Yung-Huei LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wei CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jian-Hong LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Hsien KUO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Chun LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hung NIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C13/00, G11C11/56
CPC Code(s): G11C13/0069
Abstract: a phase-change memory (pcm) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. the phase-change feature is configured to change its data state based on a write operation performed on the pcm cell. the write operation includes a reset stage and a set stage. in the reset stage, a plurality of reset current pulses are applied to the pcm cell, and the reset current pulses have increasing current amplitudes. in the set stage, a plurality of set current pulses are applied to the pcm cell, and the set current pulses exhibit an increasing trend in current amplitude. the current amplitudes of the set current pulses are smaller than those of the reset current pulses.
Inventor(s): Meng-Sheng CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C13/00, G11C11/16
CPC Code(s): G11C13/0069
Abstract: a method includes: programming a first bit of a physical unclonable function into a first memory cell; and generating, by a first memory circuit in the first memory cell, a first current indicating a logic value of the first bit. the programming the first bit includes: turning on a first switch in the first memory circuit and at least one second switch in at least one second memory circuit in the first memory cell in response to a first bit line signal, to program one of the first memory circuit and the at least one second memory circuit while rest of the first memory circuit and the at least one second memory circuit is not programmed, according to the first bit line signal. a memory device and a system are also disclosed herein.
Inventor(s): Shih-Hsien Chen of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yao Ko of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Liang-Tai Kuo of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., YingKit Felix Tsui of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C16/04, G11C16/24, H10B41/10, H10B41/23, H10B41/35, H10B41/70
CPC Code(s): G11C16/0483
Abstract: a memory device includes a first well region, a second well region, and third well regions. the second well region is interposed between the first region and the third well regions, and the third well regions are separated from one another. the memory device includes floating gates disposed over the first to third well regions, wherein each of the floating gates continuously extends from the first well region to a corresponding one of the third well regions. the memory device includes a bit line write region disposed within the second well region. the bit line write region comprises first source/drain regions on opposite sides of each floating gate. the memory device includes a bit line read region disposed within the second well region and spaced from the bit line write region. the bit line read region comprises second source/drain regions on the opposite sides of each floating gate.
Inventor(s): Chun-Ying Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Chieh Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C16/08, G11C16/04, H10B41/20, H10B43/20
CPC Code(s): G11C16/08
Abstract: a memory device includes a plurality of word lines (wls) above a substrate; a plurality of memory strings laterally isolated from each other, each of the plurality of memory strings being operatively coupled to a respective subset of the plurality of wls; and a plurality of drivers, each of the plurality of drivers being configured to control a corresponding one of the plurality of wls and including a first transistor having a first conductive type and a second transistor having a second conductive type opposite to the first conductive type.
Inventor(s): Win-San Khwa of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Lun Lu of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Jen Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Fan Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C19/28, H03K3/037, H03K19/20
CPC Code(s): G11C19/28
Abstract: the disclosure introduces a shift register is configured to enter a low power mode by disabling a portion of flip-flops (ffs) that handles upper bits of input data. the shift register includes first ff(s), second ff(s) and gating circuit. the first flip-flop (ff), includes input terminal coupled to first portion of input data. the second ff includes input terminal coupled to second portion of input data, an output terminal, a clock terminal coupled to a clock signal, a power terminal coupled to a supply power. the second portion of the input data is subsequent to the first portion of the input data. the gating circuit is coupled to the output terminal of the first ff, and configured to disable the second ff for storing the second portion of a subsequent input data according to output data currently being stored in the first ff.
Inventor(s): Ming-Sze Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yuan-Hsin Chi of Longjing Township (TW) for taiwan semiconductor manufacturing company, ltd., Yin-Tun Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu Li Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Yuan Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/32, C23C16/505
CPC Code(s): H01J37/32183
Abstract: a radio frequency (rf) match assembly for a chemical vapor deposition processing chamber. the assembly includes a top electrically insulating column and a bottom electrically insulating column. the assembly further includes a one-piece rf match strap that has a head, a main body and a body extension. the main body of the one-piece rf match strap is configured to extend through the top electrically insulating column and the bottom electrically insulating column. a flexible chamber lid strap connects the processing chamber to the top of the one-piece rf match strap.
Inventor(s): Siao-Chian HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chung CHENG of Zhongpu Shiang (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Juinn HUANG of Pushin Shiang (TW) for taiwan semiconductor manufacturing company, ltd., Tzung-Chi FU of Miaoli City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yen LEE of Jhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, B08B3/08, B08B5/04, G03F7/00, H01L21/67
CPC Code(s): H01L21/02057
Abstract: a particle removal apparatus is provided. the apparatus includes a reticle holder configured to hold a reticle, a robotic arm, and a particle removal device disposed on the robotic arm. the particle removal device includes a solution spraying module, a sucking module, and a baffle. the robotic arm and the particle removal device are configured to align with a particle on the backside of the reticle. the solution spraying module is configured to spray a solution onto the particle to remove the particle. the baffle is configured to be disposed over the backside of the reticle to define enclosed area that encompasses the particle to be removed. the sucking module is configured to suck the solution on the reticle with the particles being removed.
Inventor(s): Ru-Shang Hsiao of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chun Hsiung Tsai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Clement Hsingjen Wann of Carmel NY (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, B08B3/08, H01L21/311, H01L21/768, H01L23/535
CPC Code(s): H01L21/02074
Abstract: a semiconductor structure includes a substrate, a conductive feature over the substrate, a dielectric layer over the conductive feature and the substrate, and a structure disposed over and electrically connected to the conductive feature. the structure is partially surrounded by the dielectric layer and includes a first metal-containing layer and a second metal-contain layer surrounded by the first metal-containing layer. the first and the second metal-containing layers include different materials. a lower portion of the first metal-containing layer includes a transition metal or a transition metal nitride and an upper portion of the first metal-containing layer includes a transition metal fluoride or a transition metal chloride.
Inventor(s): Shu-Ling Liao of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Te-En Cheng of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Nai-Yu Yeh of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Han Chung of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chunyao Wang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Cheng LU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/02, H01L29/66, H01L29/78
CPC Code(s): H01L21/02216
Abstract: fabrication of semiconductor devices is provided. a chamber is evacuated to a pressure of less than about 1 torr. the chamber is heated to a temperature in excess of about 400� c. a precursor is introduced into the chamber. the precursor is decomposed with a first plasma. a first layer is deposited on a surface of the semiconductor device based on the decomposed precursor. the precursor is densified to form a first gate spacer. the precursor is introduced into the chamber subsequent to forming the first layer. the precursor is decomposed with a second plasma. a second layer is deposited on the surface of the semiconductor device based on the decomposed precursor. the deposited precursor is densified to form a second gate spacer.
Inventor(s): Tien-Shun Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Feng Nieh of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Huicheng Chang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yee-Chia Yeo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/308, G03F1/38, H01L21/265, H01L21/311, H01L21/3115, H01L21/768, H01L21/8234, H01L29/66
CPC Code(s): H01L21/3088
Abstract: a manufacturing method of a semiconductor device, comprises the following steps: providing a semiconductor substrate; forming a dummy insulation layer and a dummy electrode sequentially stacked on the semiconductor substrate; forming spacers on sidewalls of the dummy electrode; removing the dummy electrode to exposes inner sidewalls of the spacers; and performing an ion implantation process to the inner sidewalls of the spacers and the dummy insulation layer.
Inventor(s): Wei-Hao Liao of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsi-Wen Tien of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Pin-Ren Dai of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ju Lee of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/3213, H01L21/033, H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/32139
Abstract: a semiconductor structure includes a conductive feature disposed over a semiconductor substrate, a via disposed in a first interlayer dielectric (ild) layer over the conductive feature, and a metal-containing etch-stop layer (esl) disposed on the via, where the metal-containing esl includes a first metal and is resistant to etching by a fluorine-containing etchant. the semiconductor structure further includes a conductive line disposed over the metal-containing esl, where the conductive line includes a second metal different from the first metal and is etchable by the fluorine-containing etchant, and where the via is configured to interconnect the conductive line to the conductive feature. furthermore, the semiconductor structure includes a second ild layer disposed over the first ild layer.
Inventor(s): Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yian-Liang Kuo of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chung Yee of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/56, H01L21/48, H01L21/768, H01L23/00, H01L23/31, H01L23/367, H01L23/373, H01L23/522, H01L23/538, H01L23/64, H01L25/00, H01L25/065
CPC Code(s): H01L21/561
Abstract: a package structure includes a first thermal dissipation structure. the first thermal dissipation structure includes a semiconductor substrate, conductive vias, a thermal transmission structure, first capacitors, bonding pads, and bonding vias. the conductive vias are embedded in the semiconductor substrate. the thermal transmission structure is disposed over the semiconductor substrate and the conductive vias. the thermal transmission structure includes a conductive plane. the first capacitors are at least partially embedded in the thermal transmission structure. the bonding pads and the bonding vias are embedded in the thermal transmission structure. the bonding vias electrically connect the conductive vias and the bonding pads. the conductive plane is in physical contact with sidewalls of at least one of the bonding pads.
Inventor(s): Sheng-chun YANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Lung CHENG of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ming LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Chih HUANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Hsiang JUAN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Xuan-Yang ZHENG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, C23C8/24, C23C14/50, C23C16/44, C23C16/458, F15D1/02, H01J37/32, H01L21/683
CPC Code(s): H01L21/67017
Abstract: a gas flow accelerator may include a body portion, and a tapered body portion including a first end integrally formed with the body portion. the gas flow accelerator may include an inlet port connected to the body portion and to receive a process gas to be removed from a semiconductor processing tool by a main pumping line. the semiconductor processing tool may include a chuck and a chuck vacuum line to apply a vacuum to the chuck to retain a semiconductor device. the tapered body portion may be configured to generate a rotational flow of the process gas to prevent buildup of processing byproduct on interior walls of the main pumping line. the gas flow accelerator may include an outlet port integrally formed with a second end of the tapered body portion. an end portion of the chuck vacuum line may be provided through the outlet port.
Inventor(s): Wen-Hao Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsuan-Chih Chu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Yu Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, G06N20/00, H01L21/68, H01L21/683
CPC Code(s): H01L21/67265
Abstract: a device includes a movable blade having a first surface to receive a semiconductor wafer. the device can include a positional sensor to detect a position of the semiconductor wafer on a surface of the movable blade, relative to a stationary body. the movable blade can be configured to move relative to the stationary body to cause a displacement of the semiconductor wafer relative to the movable blade. the positional sensor can be coupled to the movable blade.
Inventor(s): Chieh Hsu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Guancyun Li of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Jung Chang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/677
CPC Code(s): H01L21/67736
Abstract: storage systems and method of using the same are provided. an exemplary storage system according to the present disclosure includes a storage device including a plurality of storage locations arranged in an upright stadium shape and a plurality of load ports each movable to engage any of the plurality of storage locations.
Inventor(s): Li-Zhen YU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh SU of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Lin-Yu HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi CHUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/02, H01L23/532, H01L23/535, H01L29/06, H01L29/417, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L21/7682
Abstract: a method includes forming a transistor over a substrate; forming a front-side interconnection structure over the transistor; after forming the front-side interconnection structure, removing the substrate; after removing the substrate, forming a backside via to be electrically connected to the transistor; depositing a dielectric layer to cover the backside via; forming an opening in the dielectric layer to expose the backside via; forming a spacer structure on a sidewall of the opening; after forming a spacer structure, forming a conductive feature in the opening to be electrically connected to the backside via; and after forming the conductive feature, forming an air gap in the spacer structure.
Inventor(s): Jyh-Nan Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Yu Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Shiung Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ding-I Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, C23F1/12, H01L21/02, H01L23/522, H01L23/532
CPC Code(s): H01L21/76829
Abstract: a method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.
Inventor(s): Che-Cheng CHANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/485, H01L23/528
CPC Code(s): H01L21/76831
Abstract: a device comprises a non-insulator structure, a dielectric layer, a metal via, a metal line, and a dielectric structure. the dielectric layer is over the non-insulator structure. the metal via is in a lower portion of the dielectric layer. the metal line is in an upper portion of the dielectric layer. the dielectric structure is embedded in a recessed region in the lower portion of the dielectric layer. the dielectric structure has a tapered top portion interfacing the metal via.
Inventor(s): Hsin-Yen Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Kuan Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chin Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/522, H01L23/532
CPC Code(s): H01L21/76879
Abstract: examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. in some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. the interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. a blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. an alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. the blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. the second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.
Inventor(s): Yu-Lien Huang of Jhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/033, H01L21/308, H01L21/311
CPC Code(s): H01L21/76897
Abstract: a method includes using a second hard mask layer over a gate stack to protect the gate electrode during etching a self-aligned contact. the second hard mask is formed over a first hard mask layer, where the first hard mask layer has a lower etch selectivity than the second hard mask layer.
Inventor(s): Chun Hsiung TSAI of Xinpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Feng YU of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsi YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shahaji B. MORE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chandrashekhar Prakash SAVANT of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hsin KO of Fongshan City (TW) for taiwan semiconductor manufacturing company, ltd., Clement Hsingjen WANN of Carmel NY (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/306, H01L21/3065, H01L21/324
CPC Code(s): H01L21/823431
Abstract: in a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, and an annealing operation is performed on the fin structure. in the patterning of the semiconductor layer, a damaged area is formed on a sidewall of the fin structure, and the annealing operation eliminates the damaged area.
Inventor(s): Tsung-Chieh HSIAO of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Chih Hsin YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66, H01L23/00, H01L23/48, H01L23/538
CPC Code(s): H01L22/12
Abstract: embodiments of the present disclosure relate to methods for warpage correction. particularly, embodiments of the present disclosure relate to substrate level warpage correction by depositing one or more warpage correction layers in a redistribution layer (rdl) structure, a front side warpage correction layer, and/or a back side warpage correction layer. in some embodiments, the warpage correction layer is a high stress dielectric layer. characteristics of the warpage correction layer, such as stress level, and thickness, may be determined according to the substrate level warpage and the die level packaging scheme using an auto process control program.
Inventor(s): Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56
CPC Code(s): H01L23/3114
Abstract: a method includes placing a package component over a carrier. the package component includes a device die. a core frame is placed over the carrier. the core frame forms a ring encircling the package component. the method further includes encapsulating the core frame and the package component in an encapsulant, forming redistribution lines over the core frame and the package component, and forming electrical connectors over and electrically coupling to the package component through the redistribution lines.
Inventor(s): Chien-Hsun Chen of Zhutian Township (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ling Tsai of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiun Yi Wu of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hsun Lee of Chu-tung Town (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Shi Liu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L23/498, H01L23/538
CPC Code(s): H01L23/3121
Abstract: in an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.
Inventor(s): Po-Chen LAI of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chih YEW of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L23/00, H01L23/42, H01L23/433, H01L23/498, H01L25/065
CPC Code(s): H01L23/3675
Abstract: a method of forming a semiconductor package structure is provided. the method includes disposing a first semiconductor device on an interposer substrate, disposing the interposer substrate on a carrier substrate, applying a thermal interface material on the first semiconductor device, and attaching a lid on the carrier substrate to cover the first semiconductor device. the interposer substrate is disposed between the carrier substrate and the first semiconductor device. the lid includes a lower surface having a first recess facing the first semiconductor device, and a portion of the thermal interface material is accommodated in the first recess.
Inventor(s): Chin-Shen LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ren-Zheng LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hao-Tien KAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Fong LU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/48
CPC Code(s): H01L23/481
Abstract: a semiconductor devices includes a substrate, a power grid structure, and a through via penetrating the substrate. the power grid structure includes: first and second rails extending along a first direction, a conductive wire, a third rail, a conductive via, and a connecting member. the conductive wire is between the first and second rails, and extends along the first direction. the third rail is below the first rail, the second rail and the conductive wire, and extends along a second direction perpendicular to the first direction. the conductive via is between and electrically couples the conductive wire to the third rail. the connecting member is between and electrically couples the first rail to the conductive wire. the through via extends through the substrate and along a third direction perpendicular to the first direction and the second direction. the through via is disposed on and coupled to the conductive wire.
Inventor(s): Pei-Yu Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Xuan Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/528, H01L21/02, H01L21/285, H01L21/311, H01L29/06, H01L29/417, H01L29/423, H01L29/45, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L23/5286
Abstract: in an embodiment, a device includes: a first fin; a gate structure over the first fin; a first source/drain region adjacent the gate structure; an etch stop layer over the first source/drain region; a conductive line over the etch stop layer, the conductive line isolated from the first source/drain region by the etch stop layer, a top surface of the conductive line being coplanar with a top surface of the gate structure; and a power rail contact extending through the first fin, the power rail contact connected to the first source/drain region.
Inventor(s): Ching-Yu CHANG of Yuansun Village (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da CHENG of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hui WENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, C08G73/10
CPC Code(s): H01L24/05
Abstract: a method of manufacturing a bump structure includes forming a passivation layer over a substrate. a metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. a polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. a metal bump is formed over the metal pad structure and the polyimide layer. the polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.
Inventor(s): Manikandan ARUMUGAM of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Yi YANG of () for taiwan semiconductor manufacturing company, ltd., Chien-Chih CHEN of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Mu-Han CHENG of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hsien CHENG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/08
Abstract: some implementations described herein provide a semiconductor structure. the semiconductor structure includes a first conductive structure disposed within a first layer of the semiconductor structure. the semiconductor structure includes a dielectric structure disposed within a second layer of the semiconductor structure, with the second layer being disposed on the first layer. the semiconductor structure includes a second conductive structure disposed within a recessed portion of the dielectric structure that extends to the first conductive structure, with the second conductive structure having a concave recessed portion on a top surface of the second conductive structure. the semiconductor structure includes multiple layers of conductive material disposed within the concave recessed portion of the second conductive structure.
Inventor(s): Hui-Min HUANG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da CHENG of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Hung LIN of Xinfeng Township (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Jung HSUEH of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Jun ZHAN of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Sheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/14
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a semiconductor substrate and a first conductive structure over the semiconductor substrate. the first conductive structure has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive structure. the semiconductor device structure also includes a second conductive structure over the semiconductor substrate. the second conductive structure is substantially as wide as the first conductive structure, and the second conductive structure has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive structure. the first conductive structure is closer to a center point of the semiconductor substrate than the second conductive structure. the second protruding portion is wider than the first protruding portion, and bottoms of the first protruding portion and the second protruding portion are substantially level with each other.
Inventor(s): Kuo-Chiang Ting of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsi Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Yun Hou of Jubei City (TW) for taiwan semiconductor manufacturing company, ltd., Tu-Hao Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Yu Yeh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/48, H01L21/56, H01L21/683, H01L23/31, H01L23/498, H01L23/538, H01L25/00, H01L25/18
CPC Code(s): H01L24/24
Abstract: a method includes bonding a first device die and a second device die to an interconnect die. the interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. the interconnect die electrically connects the first device die to the second device die. the method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
Inventor(s): Li-Hsien Huang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Chun Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., SyuFong Li of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Pin Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jun He of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L21/66, H01L21/683, H01L23/48
CPC Code(s): H01L24/27
Abstract: in an embodiment, a method includes attaching a first package component to a first carrier, the first package component comprising: an aluminum pad disposed adjacent to a substrate; a sacrificial pad disposed adjacent to the substrate, the sacrificial pad comprising a major surface opposite the substrate, a protrusion of the sacrificial pad extending from the major surface; and a dielectric bond layer disposed around the aluminum pad and the sacrificial pad; attaching a second carrier to the first package component and the first carrier, the first package component being interposed between the first carrier and the second carrier; removing the first carrier; planarizing the dielectric bond layer to comprise a top surface being coplanar with the protrusion; and etching a portion of the protrusion.
Inventor(s): Kai Jun Zhan of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Fu Kao of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Chun Lee of New Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Da Cheng of Taoyuan (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Shien Chen of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/81
Abstract: a method includes attaching a die to a thermal compression bonding (tcb) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the tcb head.
Inventor(s): Chen-Hua Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei Ling Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chieh-Yen Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/16, H01L23/00
CPC Code(s): H01L25/16
Abstract: in an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.
Inventor(s): Chuei-Tang Wang of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Hao Tsai of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chun Tang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/16, H01L21/56, H01L23/00, H01L23/31, H01L23/48, H01L23/552, H01L23/66, H01Q9/04, H01Q9/16, H01Q21/06, H01Q21/08
CPC Code(s): H01L25/16
Abstract: a package structure includes a semiconductor die, an antenna substrate structure, a redistribution layer. the semiconductor die laterally encapsulated by a first encapsulant. the antenna substrate structure disposed over the semiconductor die, wherein the antenna substrate structure includes a first type of antenna, and a second type of antenna disposed on a side of the antenna substrate structure facing away from the semiconductor die. the redistribution layer disposed between the semiconductor die and the antenna substrate structure. the semiconductor die, the first type of antenna, and the second type of antenna are electrically coupled through the redistribution layer. the polarization of radiation emitted by the first type of antenna is perpendicular to a polarization of radiation emitted by the second type of antenna.
Inventor(s): Chih-Hung Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Shuan Li of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih Chieh Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Zi-Ang Su of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ju Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L21/8234, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L27/0266
Abstract: the present disclosure provides a semiconductor device. the semiconductor device includes a semiconductor substrate and an epitaxial stack disposed above the semiconductor substrate. the epitaxial stack includes first and second type epitaxial layers, the first and second type epitaxial layers having different material compositions. the first and second type epitaxial layers are alternatingly disposed in a vertical direction. the semiconductor device also includes a first doped region in the epitaxial stack and a second doped region in the epitaxial stack. the first doped region has a first dopant of a first conductivity type. the second doped region has a second dopant of a second conductivity type opposite the first conductivity type. the semiconductor device also includes first and second gate stacks disposed above the epitaxial stack. a portion of the first doped region and a portion of the second doped region are between the first and second gate stacks.
Inventor(s): Shu-Hui SU of Tucheng City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Li CHENG of Hsin Chu (TW) for taiwan semiconductor manufacturing company, ltd., YingKit Felix TSUI of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L23/00, H01L23/522
CPC Code(s): H01L27/0292
Abstract: some implementations herein describe apparatuses and techniques related to a semiconductor die package including a first integrated circuit die including capacitor circuitry bonded with a second integrated circuit die including logic circuitry. the semiconductor die package may include discharge paths incorporated into a seal ring structure spanning the first integrated circuit die and the second integrated circuit die. the discharge paths may lead to a power management integrated circuit included in the second integrated circuit die. during a bonding of the first integrated circuit die and the second integrated circuit die, the discharge paths incorporated into the seal ring structure may route an electrical discharge from the capacitor circuitry of the first integrated circuit die to the power management integrated circuit.
Inventor(s): Te-Hsin CHIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kam-Tou SIO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Wei FANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jiann-Tyng TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, G06F30/392, H01L21/033, H01L21/8234, H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H01L27/0886
Abstract: disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including n nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including m nanosheets, wherein n is different from m in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.
Inventor(s): Kuan-Jung Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., I-Chih Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Mu Huang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kai-Di Wu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Feng Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Chun Kuan of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L21/8238, H01L27/092, H01L29/10, H01L29/423, H01L29/66, H01L29/78
CPC Code(s): H01L27/0886
Abstract: a semiconductor device includes a semiconductor substrate having a first region and a second region, insulators, gate stacks, and first and second s/ds. the first and second regions respectively includes at least one first semiconductor fin and at least one second semiconductor fin. a width of a middle portion of the first semiconductor fin is equal to widths of end portions of the first semiconductor fin. a width of a middle portion of the second semiconductor fin is smaller than widths of end portions of the second semiconductor fin. the insulators are disposed on the semiconductor substrate. the first and second semiconductor fins are sandwiched by the insulators. the gate stacks are over a portion of the first semiconductor fin and a portion of the second semiconductor fin. the first and second s/ds respectively covers another portion of the first semiconductor fin and another portion of the second semiconductor fin
Inventor(s): Ting-Yun Wu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Chien Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/822, H01L21/8238, H01L29/66
CPC Code(s): H01L27/0922
Abstract: a method for forming complementary finfet (cfet) in a stacked configuration includes forming a recess in a stacked fin, growing a first epitaxial structure in the recess, etching the first epitaxial structure to remove a portion of the first epitaxial structure, forming a first isolation structure over the first epitaxial structure, and forming a second epitaxial structure over the first isolation structure. in another method, a dummy gate electrode over the stacked fin is etched, a first gate electrode deposited over the stacked fin, a portion of the first gate electrode recessed, and a second gate electrode formed over the first gate electrode. a cfet device includes a second channel region stacked over a first channel region, associated pairs of epitaxial structures on opposing sides of each of the first and second channel regions, and associated gate electrodes for each of the first and second channel regions.
Inventor(s): Cheng-Ming Lin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yen Woon of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Szuya Liao of Zhubei Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/40, H01L29/51
CPC Code(s): H01L27/0922
Abstract: a dipole layer is formed over a semiconductor channel region. a doped gate dielectric layer is formed over the dipole layer. the doped gate dielectric layer contains an amorphous material. via an annealing process, the amorphous material of the doped gate dielectric layer is converted into a material with at least partially crystal phases. after the doped gate dielectric layer is converted into the layer with partially crystal phases, a metal-containing gate electrode is formed over the doped gate dielectric layer.
Inventor(s): Mrunal A. Khaderbad of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ziwei Fang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Chu Lin of Ping-Tung (TW) for taiwan semiconductor manufacturing company, ltd., Hsueh Wen Tsau of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8234, H01L21/8238
CPC Code(s): H01L27/0924
Abstract: an integrated circuit (ic) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. a gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. a first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. a second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 ev.
Inventor(s): Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Min Cao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Wen Chang of Jhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/06, H01L29/66, H01L29/78
CPC Code(s): H01L27/0924
Abstract: various embodiments of the present disclosure are directed towards an integrated chip (ic). the ic includes a first fin projecting vertically from a semiconductor substrate. a second fin projects vertically from the semiconductor substrate, where the second fin is spaced from the first fin, and where the first fin has a first uppermost surface that is disposed over a second uppermost surface of the second fin. a nanostructure stack is disposed over the second fin and vertically spaced from the second fin, where the nanostructure stack comprises a plurality of vertically stacked semiconductor nanostructures. a pair of first source/drain regions is disposed on the first fin, where the first source/drain regions are disposed on opposite sides of an upper portion of the first fin. a pair of second source/drain regions is disposed on the second fin, where the second source/drain regions are disposed on opposite sides of the nanostructure stack.
Inventor(s): Ta-Yuan Kung of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Liang Chu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Wen Albert Yao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Fei-Yun Chen of Hinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Ta Lei of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Ruey-Hsin Liu of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chang Jong of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L21/302, H01L29/06, H01L29/40, H01L29/49, H01L29/66, H01L29/78
CPC Code(s): H01L29/0847
Abstract: an integrated chip including a first source/drain region and a second source/drain region in a semiconductor substrate and laterally spaced apart along a top surface of the substrate. a gate dielectric layer is over the substrate and extends laterally between the first source/drain region and the second source/drain region. a thickness of the gate dielectric layer along a first sidewall of the gate dielectric layer is less than an average thickness of the gate dielectric layer. a trench isolation layer extends along gate dielectric layer. a first sidewall of the trench isolation layer extends along the first sidewall of the gate dielectric layer. a gate layer is directly over the gate dielectric layer and between the first source/drain region and the second source/drain region. a first sidewall of the gate layer is directly over the gate dielectric layer and laterally setback from the first sidewall of the gate dielectric layer.
Inventor(s): Yi-Syuan Siao of Changhua City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Han Chou of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Yu Lin of Yilan County (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Ting Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Shun Chang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-I Kuan of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Su-Hao Liu of Jhongpu Township (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/8238, H01L27/092, H01L29/06, H01L29/08, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/41733
Abstract: in an embodiment, a device includes: a first semiconductor nanostructure; a second semiconductor nanostructure adjacent the first semiconductor nanostructure; a first source/drain region on a first sidewall of the first semiconductor nanostructure; a second source/drain region on a second sidewall of the second semiconductor nanostructure, the second source/drain region completely separated from the first source/drain region; and a source/drain contact between the first source/drain region and the second source/drain region.
Inventor(s): Po-Hsien Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jr-Hung Li of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Chun Huang of Hsin-Chu city (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Ting Ko of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Jr-Yu Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wan-Chen Hsieh of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L29/08, H01L29/66, H01L29/78
CPC Code(s): H01L29/41791
Abstract: a semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (s/d) region and a contact. the s/d region is located in the substrate and on a side of the gate structure. the contact lands on and connected to the s/d region. the contact wraps around the s/d region.
Inventor(s): Jyun-Hong HUANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Che CHIANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Chih KAO of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/06, H01L29/66
CPC Code(s): H01L29/42392
Abstract: a method for forming a semiconductor structure is provided. the method for forming the semiconductor structure includes forming an active region extending in a first horizontal direction, forming an isolation structure surrounding the active region, forming a gate dielectric layer over the active region and the isolation structure, forming a gate electrode layer nested within the gate dielectric layer, and removing the gate electrode layer and a first portion of the gate dielectric layer over the isolation structure to form a trench. a second portion of the gate dielectric layer over the active region is left to form first protection features. the method further includes depositing a dielectric layer in the trench.
Inventor(s): Chun-Yuan CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Yu WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Chieh SU of Changhua (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/45, H01L21/28, H01L23/535, H01L29/40, H01L29/423, H01L29/786
CPC Code(s): H01L29/456
Abstract: the present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. the semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.
Inventor(s): Chun-An Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yuan Lu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Ching Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Li Su of HsinChu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, A61B5/15, G01N1/14, G01N33/49, H01L21/02, H01L21/8238, H01L27/092, H01L29/04, H01L29/66
CPC Code(s): H01L29/785
Abstract: the present application provides a semiconductor device and the method of making the same. the method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. the forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. the forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
Inventor(s): Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Ting Lan of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L29/06, H01L29/417, H01L29/423, H01L29/66
CPC Code(s): H01L29/78618
Abstract: a semiconductor transistor device including a channel structure, gate structure, a first source/drain structure, a second source/drain structure, and a back-side source/drain contact. the gate structure overlies the channel structure. the first source/drain structure and the second source/drain structure are disposed on opposite endings of the channel structure. the back-side source/drain contact is disposed under the first source/drain structure. a line lies across the gate structure and the first source/drain structure. the line is parallel to an upper surface of the gate structure.
Inventor(s): Chih-Yang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L27/088, H01L29/06, H01L29/08, H01L29/423
CPC Code(s): H01L29/78696
Abstract: an integrated circuit and a formation method thereof are provided. the integrated circuit includes first and second gate structures; first and second channel structures, laterally penetrating through the first and second gate structures, respectively; first and second source/drain structures, disposed between the first and second gate structures, and in lateral contact with the first and second channel structures, respectively; an isolation wall, extending in between the first and second source/drain structures, and cutting each of the first and second gate structures into separate portions; and a lateral contact structure, extending in between the first and second gate structures, and connecting the first source/drain structure to the second source/drain structure without being cut by the isolation wall.
Inventor(s): Cheng-Wei WU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chi LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/872, H01L21/302, H01L29/06, H01L29/66
CPC Code(s): H01L29/872
Abstract: a method of forming a semiconductor device includes providing a first isolation feature in a substrate, where the first isolation feature defines and isolates a cathode region of a schottky barrier diode (sbd) from an anode region of the sbd. in some embodiments, the method further includes forming a patterned resist protective oxide (rpo) layer over the first isolation feature. thereafter, the method further includes forming a first metal contact that extends through the patterned rpo layer and extends into the first isolation feature.
Inventor(s): Huan-Neng CHEN of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Fen HU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Yu LI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K5/01, H03K5/00, H03K19/20
CPC Code(s): H03K5/01
Abstract: in some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. in some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. in some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.
Inventor(s): Ming Hsien TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K17/0812, H02M1/08, H02M1/32
CPC Code(s): H03K17/08122
Abstract: an ic includes power and reference nodes, a protection circuit, and a gate driver. the protection circuit includes a series of diode-configured enhancement-mode n-type hemts coupled between the power and reference nodes and including a voltage tap, a first enhancement-mode n-type hemt including a gate coupled to the voltage tap and a source terminal coupled to the reference node, and a second enhancement-mode n-type hemt including a gate coupled to a drain terminal of the first n-type hemt and a source terminal coupled to the reference node. the gate driver includes a third enhancement-mode n-type hemt including a gate coupled to a drain terminal of the second n-type hemt, a fourth enhancement-mode n-type hemt including a gate coupled to a source terminal of the third n-type hemt and a source terminal coupled to the reference node, and an output terminal coupled to a drain terminal of the fourth n-type hemt.
Inventor(s): Yi-An Lai of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chan-Hong Chern of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd., Cheng-Hsiang Hsieh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03K17/0812, H02H9/04
CPC Code(s): H03K17/08128
Abstract: a switching circuit includes a main circuit including a number of first transistors. the main circuit has a first node, a second node, and a third node and is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. the switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit. the auxiliary circuit includes a second transistor. a breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the number of first transistors.
Inventor(s): Chih-Chuan Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hsiu Hsu of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chun Keng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lien Jung Hung of Taipei (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00
CPC Code(s): H10B10/12
Abstract: a semiconductor device includes a first transistor and a well strap feature disposed over a doped region of a first type dopant. the first transistor includes a first gate structure engaging a first channel region and a first epitaxial feature abutting the first channel region. the well-strap feature incudes a plurality of first nanostructures vertically stacked, a second gate structure wrapping around each of the first nanostructures, and a second epitaxial feature abutting the first nanostructures. the well-strap feature is configured to bias the doped region by electrically connecting the second epitaxial feature to a bias voltage.
Inventor(s): Shih-Hao Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kian-Long Lim of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chuan Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Pao of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jing-Yi Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, H01L21/02, H01L21/3065, H01L21/308, H01L21/8238, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H10B10/125
Abstract: a substrate includes a first doped region having a first type dopant, and a second doped region having a second type dopant and adjacent to the first doped region. a stack is formed that includes first layers and second layers alternating with each other. the first and second layers each have a first and second semiconductor material, respectively. the second semiconductor material is different than the first semiconductor material. a mask element is formed that has an opening in a channel region over the second doped region. a top portion of the stack not covered by the mask element is recessed. the stack is then processed to form a first and a second transistors. the first transistor has a first number of first layers. the second transistor has a second number of first layers. the first number is greater than the second number.
Inventor(s): Chern-Yow Hsu of Chu-Bei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B61/00, H10N50/01, H10N50/80
CPC Code(s): H10B61/22
Abstract: the present disclosure relates to a method of forming an integrated chip. the method includes forming a magnetic tunnel junction (mtj) stack over a bottom electrode layer. a sacrificial dielectric is formed over the mtj stack. the sacrificial dielectric is patterned to form a cavity. a top electrode material is formed within the cavity and a mask is formed over the top electrode material. the top electrode material extends from directly below the mask to laterally past an outermost sidewall of the mask. the sacrificial dielectric is removed. the mtj stack is patterned according to the top electrode material and the mask to form an mtj after removing the sacrificial dielectric. an etchant that is used to pattern the mtj stack etches the top electrode material with the mask in place.
Inventor(s): Chun-Chieh MO of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Chi KUO of Yangmei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Hao HUNG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B63/00, H10B61/00, H10N50/01, H10N50/10, H10N50/80, H10N50/85, H10N70/00, H10N70/20
CPC Code(s): H10B63/24
Abstract: a memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.
Inventor(s): Hung-Li Chiang of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Ching Cheng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Piao Chiu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng Chen of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B63/00, G11C13/00, H10N70/00
CPC Code(s): H10B63/80
Abstract: the present disclosure relates to an integrated chip structure. the integrated chip structure includes a plurality of memory stacks disposed over a substrate and respectively having a plurality of conductive segments stacked onto one another. one or more data storage structures are on the plurality of memory stacks, one or more selectors are over the one or more data storage structures, and an upper conductor over the one or more selectors. the plurality of memory stacks include a first memory stack, a second memory stack, and a third memory stack. the first memory stack and the third memory stack are closest memory stacks to opposing sides of the second memory stack. the first memory stack is closer to the second memory stack than the third memory stack.
Inventor(s): Yu-Jen CHIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Tang WU of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Hua WU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Szu LEE of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Yu WU of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/01, H10B61/00, H10N50/80
CPC Code(s): H10N50/01
Abstract: a method of manufacturing a semiconductor device includes: forming a substrate over the substrate, the substrate defining a logic region and a memory region; depositing a bottom electrode layer across the logic region and the memory region; depositing a magnetic tunnel junction (mtj) layer over the bottom electrode layer; depositing a first conductive layer over the mtj layer; depositing a sacrificial layer over the first conductive layer; etching the sacrificial layer in the memory region to expose the first conductive layer in the memory region while keeping the first conductive layer in the logic region covered; depositing a second conductive layer in the memory region and the logic region; patterning the second conductive layer to expose the mtj layer in the memory region; and etching the patterned second conductive layer and the mtj layer to form a top electrode and an mtj, respectively, in the memory region.
Taiwan Semiconductor Manufacturing Company, Ltd. patent applications on August 1st, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- G01N21/88
- H01L21/66
- CPC G01N21/88
- Taiwan semiconductor manufacturing company, ltd.
- G01R31/28
- H01L27/02
- CPC G01R31/2879
- G05F1/595
- G05F1/575
- H03K19/0175
- CPC G05F1/595
- G06F1/10
- G06F1/12
- CPC G06F1/10
- CPC G06F1/12
- G06F12/0804
- G06F12/06
- G11C11/4093
- G11C11/4096
- CPC G06F12/0804
- G06F30/392
- G06F30/394
- H03K3/356
- CPC G06F30/392
- G06F30/39
- G06F30/398
- G06F119/18
- G06F30/30
- G06F119/06
- G06F119/12
- CPC G06F30/398
- G11C5/06
- H01L23/522
- H01L23/528
- H10B10/00
- CPC G11C5/063
- G11C11/16
- H10B61/00
- H10N50/01
- H10N50/80
- H10N50/85
- CPC G11C11/1659
- G11C11/417
- G06F7/544
- G11C11/412
- CPC G11C11/417
- G11C11/419
- CPC G11C11/419
- G11C13/00
- CPC G11C13/0064
- G11C11/56
- CPC G11C13/0069
- G11C16/04
- G11C16/24
- H10B41/10
- H10B41/23
- H10B41/35
- H10B41/70
- CPC G11C16/0483
- G11C16/08
- H10B41/20
- H10B43/20
- CPC G11C16/08
- G11C19/28
- H03K3/037
- H03K19/20
- CPC G11C19/28
- H01J37/32
- C23C16/505
- CPC H01J37/32183
- H01L21/02
- B08B3/08
- B08B5/04
- G03F7/00
- H01L21/67
- CPC H01L21/02057
- H01L21/311
- H01L21/768
- H01L23/535
- CPC H01L21/02074
- H01L29/66
- H01L29/78
- CPC H01L21/02216
- H01L21/308
- G03F1/38
- H01L21/265
- H01L21/3115
- H01L21/8234
- CPC H01L21/3088
- H01L21/3213
- H01L21/033
- H01L23/532
- CPC H01L21/32139
- H01L21/56
- H01L21/48
- H01L23/00
- H01L23/31
- H01L23/367
- H01L23/373
- H01L23/538
- H01L23/64
- H01L25/00
- H01L25/065
- CPC H01L21/561
- C23C8/24
- C23C14/50
- C23C16/44
- C23C16/458
- F15D1/02
- H01L21/683
- CPC H01L21/67017
- G06N20/00
- H01L21/68
- CPC H01L21/67265
- H01L21/677
- CPC H01L21/67736
- H01L29/06
- H01L29/417
- H01L29/423
- H01L29/786
- CPC H01L21/7682
- C23F1/12
- CPC H01L21/76829
- H01L23/485
- CPC H01L21/76831
- CPC H01L21/76879
- CPC H01L21/76897
- H01L21/306
- H01L21/3065
- H01L21/324
- CPC H01L21/823431
- H01L23/48
- CPC H01L22/12
- CPC H01L23/3114
- H01L23/498
- CPC H01L23/3121
- H01L23/42
- H01L23/433
- CPC H01L23/3675
- CPC H01L23/481
- H01L21/285
- H01L29/45
- CPC H01L23/5286
- C08G73/10
- CPC H01L24/05
- CPC H01L24/08
- CPC H01L24/14
- H01L25/18
- CPC H01L24/24
- CPC H01L24/27
- CPC H01L24/81
- H01L25/16
- CPC H01L25/16
- H01L23/552
- H01L23/66
- H01Q9/04
- H01Q9/16
- H01Q21/06
- H01Q21/08
- CPC H01L27/0266
- CPC H01L27/0292
- H01L27/088
- CPC H01L27/0886
- H01L21/8238
- H01L27/092
- H01L29/10
- H01L21/822
- CPC H01L27/0922
- H01L29/40
- H01L29/51
- CPC H01L27/0924
- H01L29/08
- H01L21/302
- H01L29/49
- CPC H01L29/0847
- H01L29/775
- CPC H01L29/41733
- CPC H01L29/41791
- CPC H01L29/42392
- H01L21/28
- CPC H01L29/456
- A61B5/15
- G01N1/14
- G01N33/49
- H01L29/04
- CPC H01L29/785
- CPC H01L29/78618
- CPC H01L29/78696
- H01L29/872
- CPC H01L29/872
- H03K5/01
- H03K5/00
- CPC H03K5/01
- H03K17/0812
- H02M1/08
- H02M1/32
- CPC H03K17/08122
- H02H9/04
- CPC H03K17/08128
- CPC H10B10/12
- CPC H10B10/125
- CPC H10B61/22
- H10B63/00
- H10N50/10
- H10N70/00
- H10N70/20
- CPC H10B63/24
- CPC H10B63/80
- CPC H10N50/01
