TEXAS INSTRUMENTS INCORPORATED patent applications on October 17th, 2024
Patent Applications by TEXAS INSTRUMENTS INCORPORATED on October 17th, 2024
TEXAS INSTRUMENTS INCORPORATED: 19 patent applications
TEXAS INSTRUMENTS INCORPORATED has applied for patents in the areas of G06F9/30 (3), G06F9/38 (3), G06F13/16 (3), G06F12/0831 (2), G06F12/0811 (2) G01F1/66 (1), H01F27/40 (1), H04W40/248 (1), H04N19/82 (1), H04N9/312 (1)
With keywords such as: data, cache, die, side, processor, node, butterfly, controller, circuit, and coupled in patent application abstracts.
Patent Applications by TEXAS INSTRUMENTS INCORPORATED
20240344862. ULTRASONIC FLOW METER_simplified_abstract_(texas instruments incorporated)
Inventor(s): Anand Dabak of Plano TX (US) for texas instruments incorporated, Clive Bittlestone of Allen TX (US) for texas instruments incorporated
IPC Code(s): G01F1/66, G01F1/667, G01F15/061, H04Q9/00
CPC Code(s): G01F1/66
Abstract: a flow meter ultrasonically measures fluid velocity in a pipe and ultrasonically transmits fluid flow data along the pipe. an ultrasonic transducer used for fluid velocity measurement may optionally also be used for communication of flow data, and optionally, the ultrasonic frequency for fluid velocity measurement may be the same as the ultrasonic frequency for communication of flow data.
Inventor(s): Lee D. Whetsel of Parker TX (US) for texas instruments incorporated
IPC Code(s): G01R31/26, G01R31/3177, G01R31/3185
CPC Code(s): G01R31/2607
Abstract: a test control port (tcp) includes a state machine sm, an instruction register ir, data registers drs, a gating circuit and a tdo mx. the sm inputs tci signals and outputs control signals to the ir and to the dr. during instruction or data scans, the ir or drs are enabled to input data from tdi and output data to the tdo mx and the top surface tdo signal. the bottom surface tci inputs may be coupled to the top surface tco signals via the gating circuit. the top surface tdi signal may be coupled to the bottom surface tdo signal via tdo mx. this allows concatenating or daisy-chaining the ir and dr of a tcp of a lower die with an ir and dr of a tcp of a die stacked on top of the lower die.
Inventor(s): Devanathan Varadarajan of Allen TX (US) for texas instruments incorporated, Benjamin Niewenhuis of Richardson TX (US) for texas instruments incorporated
IPC Code(s): G01R31/317, G01R31/28, G01R31/3177, G01R31/3185
CPC Code(s): G01R31/31703
Abstract: an example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor.
Inventor(s): Pankaj GUPTA of Dausa (IN) for texas instruments incorporated, Karthik SUBBURAJ of Bangalore (IN) for texas instruments incorporated, Sujaata RAMALINGAM of Bangalore (IN) for texas instruments incorporated, Karthik RAMASUBRAMANIAN of Bangalore (IN) for texas instruments incorporated, Indu PRATHAPAN of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F7/49, G06F7/501, G06F17/14
CPC Code(s): G06F7/49
Abstract: a system includes radix-2butterfly stages, each including first and second radix-2butterfly circuits, in which the first radix-2butterfly circuit of a first radix-2butterfly stage includes a data input coupled to a system data input, and one of the first radix-2butterfly circuit and the second radix-2butterfly circuit of a last radix-2butterfly stage includes a data output coupled to a system data output. the system further includes a radix-3 butterfly circuit including a data input coupled to the system data input and a data output selectively couplable to a data input of one of the first or second radix-2butterfly circuits of a second or later radix-2butterfly stage based on a particular point transform to be performed by the system. a set of memories are used by either the first radix-2butterfly stage or the radix-3 butterfly circuit, depending on the particular point transform.
Inventor(s): Jayasree Sankaranarayanan of Kerala (IN) for texas instruments incorporated, Dipan Kumar Mandal of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F9/38, G06F9/30
CPC Code(s): G06F9/383
Abstract: this disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector simd processor. the invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. this enables data processing by vector single instruction multiple data (simd) operations. this vector destination register load can be repeated if the tables store more used data. new data can be loaded into the original tables if appropriate. a level one memory is preferably partitioned as part data cache and part directly addressable memory. the look up table memory is stored in the directly addressable memory.
20240345868. PSEUDO-RANDOM WAY SELECTION_simplified_abstract_(texas instruments incorporated)
Inventor(s): Abhijeet Ashok CHACHAD of Plano TX (US) for texas instruments incorporated, David Matthew THOMPSON of Dallas TX (US) for texas instruments incorporated
IPC Code(s): G06F9/46, G06F9/30, G06F9/38, G06F9/448, G06F9/48, G06F9/54, G06F11/30, G06F12/0804, G06F12/0811, G06F12/0813, G06F12/0817, G06F12/0831, G06F12/0855, G06F12/0871, G06F12/0888, G06F12/0891, G06F12/12, G06F12/121, G06F13/16
CPC Code(s): G06F9/467
Abstract: a method includes receiving a first request to allocate a line in an n-way set associative cache and, in response to a cache coherence state of a way indicating that a cache line stored in the way is invalid, allocating the way for the first request. the method also includes, in response to no ways in the set having a cache coherence state indicating that the cache line stored in the way is invalid, randomly selecting one of the ways in the set. the method also includes, in response to a cache coherence state of the selected way indicating that another request is not pending for the selected way, allocating the selected way for the first request.
Inventor(s): Hetul Sanghvi of Richardson TX (US) for texas instruments incorporated, Niraj Nandan of Plano TX (US) for texas instruments incorporated, Mihir Narendra Mody of Bangalore (IN) for texas instruments incorporated, Kedar Satish Chitnis of Bangalore (IN) for texas instruments incorporated
IPC Code(s): G06F9/48, G06F9/50
CPC Code(s): G06F9/4812
Abstract: systems and method are provided for flexibly configuring task schedulers and respectively associated data processing nodes to execute threads of tasks using a hardware thread scheduler (hts). the data processing nodes may be hardware accelerators, channels of a direct memory access circuit and external nodes such as a processor executing software instructions. each hardware accelerator is coupled to a respective hardware task scheduler, each channel is coupled to a respective channel task scheduler, and each external node is coupled to a proxy task scheduler. the task schedulers communicate via pending and decrement signals with a hardware scheduler crossbar. with this arrangement, the hts couples a first subset of task schedulers in a first data processing order with the associated data processing nodes performing the tasks, and couples a second subset of task schedulers in a second data processing order with the associated data processing nodes performing the tasks.
Inventor(s): Abhijeet Ashok Chachad of Plano TX (US) for texas instruments incorporated, David Matthew Thompson of Dallas TX (US) for texas instruments incorporated, Naveen BHORIA of Plano TX (US) for texas instruments incorporated, Peter Michael HIPPLEHEUSER of Murphy TX (US) for texas instruments incorporated
IPC Code(s): G06F12/0811, G06F9/30, G06F9/38, G06F9/46, G06F9/54, G06F11/30, G06F12/0808, G06F12/0815, G06F12/0817, G06F12/0831, G06F12/084, G06F12/0895, G06F12/128, G06F13/16
CPC Code(s): G06F12/0811
Abstract: an apparatus includes a cpu core and a l1 cache subsystem including a l1 main cache, a l1 victim cache, and a l1 controller. the apparatus includes a l2 cache subsystem coupled to the l1 cache subsystem by a transaction bus and a tag update bus. the l2 cache subsystem includes a l2 main cache, a shadow l1 main cache, a shadow l1 victim cache, and a l2 controller. the l2 controller receives a message from the l1 controller over the tag update bus, including a valid signal, an address, and a coherence state. in response to the valid signal being asserted, the l2 controller identifies an entry in the shadow l1 main cache or the shadow l1 victim cache having an address corresponding to the address of the message and updates a coherence state of the identified entry to be the coherence state of the message.
20240345970. PCIE PERIPHERAL SHARING_simplified_abstract_(texas instruments incorporated)
Inventor(s): Sriramakrishnan GOVINDARAJAN of Bengaluru (IN) for texas instruments incorporated, Kishon Vijay Abraham ISRAEL VIJAYPONRAJ of Bengaluru (IN) for texas instruments incorporated, Mihir Narendra MODY of Bengaluru (IN) for texas instruments incorporated, Jason A.T. Jones of Richmond TX (US) for texas instruments incorporated
IPC Code(s): G06F13/16, G06F12/10, G06F13/40, G06F13/42
CPC Code(s): G06F13/1668
Abstract: a peripheral proxy subsystem provides routing mechanisms to allow multiple hosts to communicate with multiple functions, physical and virtual, of a single root i/o virtualization (sr-iov) peripheral, which may include a physical function and a plurality of virtual functions associated with the physical function. the peripheral proxy subsystem, which may be embodied as a controller, includes a first endpoint interface; a second endpoint interface; and a single root controller interface configured to couple to the sr-iov peripheral. the controller is configured to be able to present through the single root controller interface: a first subset of the plurality of virtual functions through a first cloned instance of the physical function at the first endpoint interface; and a second subset of the plurality of virtual functions through a second cloned instance of the physical function at the second endpoint interface.
Inventor(s): Aishwarya Dubey of Plano TX (US) for texas instruments incorporated, Hetul Sanghvi of Murphy TX (US) for texas instruments incorporated
IPC Code(s): G06T7/269, G06T3/40, G06V10/25, G06V10/50, G06V20/40, G06V20/56, G06V20/64
CPC Code(s): G06T7/269
Abstract: a method for identifying regions of interest (rois) includes receiving, by a processor from a video camera, a video image and computing, by the processor, an optical flow image, based on the video image. the method also includes computing, by the processor, a magnitude of optical flow image based on the video image and computing a histogram of optical flow magnitudes (hofm) image for the video image based on the magnitude of optical flow image. additionally, the method includes generating, by the processor, a mask indicating rois of the video image, based on the hofm.
Inventor(s): Yi YAN of San Jose CA (US) for texas instruments incorporated, Hidetoshi INOUE of Richardson TX (US) for texas instruments incorporated
IPC Code(s): H01F27/40, H01F27/06, H01F27/24, H01F27/29, H01F41/04
CPC Code(s): H01F27/40
Abstract: an apparatus includes a magnetic core and an inductor. the magnetic core has a cylindrical boss and a base plate. the cylindrical boss has a first end and a second end. the base plate extends perpendicularly from the first end of the cylindrical boss. the base plate has a top side and a bottom side. the inductor includes a coil, a first terminal, and a second terminal. the coil is disposed on the top side of the base plate about the cylindrical boss. the first terminal is wrapped from the top side of the base plate to the bottom side of the base plate. the second terminal is wrapped from the top side of the base plate to the bottom side of the base plate.
Inventor(s): HUAY YANN TAY of MELAKA (ML) for texas instruments incorporated, WEI LI JULIEN MOK of MELAKA (ML) for texas instruments incorporated, YOU CHYE HOW of MELAKA TENGAH (ML) for texas instruments incorporated
IPC Code(s): H01L23/495, H01L21/56, H01L23/00, H01L23/31
CPC Code(s): H01L23/49541
Abstract: an integrated circuit (ic) package includes a mold compound. a first interconnect of the ic package is encased in the mold compound. the first interconnect includes a first set of leads protruding from a first side of the mold compound along a first row and a second set of leads protruding from a second side of the mold compound along a second row, wherein the first row and the second row are in a first plane. a second interconnect of the ic package is also encased in the mold compound. the second interconnect includes a third set of leads protruding from the first side of the mold compound along a third row and a fourth set of leads protruding from the second side of the mold compound along a fourth row. the third row and the fourth row are in a second plane.
Inventor(s): Anindya Poddar of Sunnyvale CA (US) for texas instruments incorporated, Ashok Surendra Prabhu of San Jose CA (US) for texas instruments incorporated, Edgar Dorotyao Balidoy of Virac (PH) for texas instruments incorporated, Hau Nguyen of San Jose CA (US) for texas instruments incorporated, Makoto Yoshino of Beppu-city (JP) for texas instruments incorporated, MING LI of Chengdu-city (CN) for texas instruments incorporated
IPC Code(s): H01L23/498, H01L21/48, H01L21/56, H01L23/00, H05K1/02
CPC Code(s): H01L23/49861
Abstract: a described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. the leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. a semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.
Inventor(s): Takashi Shiga of Tsukuba (JP) for texas instruments incorporated, Hiromi Endoh of Inashiki City (JP) for texas instruments incorporated, Tatsuya Tominari of Plano TX (US) for texas instruments incorporated
IPC Code(s): H01L29/36, H01L21/265
CPC Code(s): H01L29/36
Abstract: the present disclosure generally relates to reducing auto-doping in a semiconductor structure. in an example, semiconductor device structure includes a semiconductor substrate, a first epitaxial layer, and a second epitaxial layer. the semiconductor substrate has a first region and a second region. the first region includes a doped layer doped with a first dopant in the semiconductor substrate. the first epitaxial layer is on the doped layer in the first region. the second epitaxial layer is on the first epitaxial layer in the first region and on the semiconductor substrate in the second region.
Inventor(s): Runhua Chen of Plano TX (US) for texas instruments incorporated, Anthony Edet Ekpenyong of Houston TX (US) for texas instruments incorporated
IPC Code(s): H04L5/00, H04L1/00, H04L5/14, H04W28/02, H04W72/21, H04W72/54, H04W72/542, H04W76/00
CPC Code(s): H04L5/0073
Abstract: a method of operating a time division duplex (tdd) wireless communication system is disclosed. the method includes establishing communications with a remote transceiver. a subframe configuration including static and flexible subframes is determined and transmitted to the remote transceiver. a channel state information (csi) report is received from the remote transceiver in response to the subframe configuration.
Inventor(s): Harsh D. JHAVERI of Wylie TX (US) for texas instruments incorporated, Brenda MCWILLIAMS of Wylie TX (US) for texas instruments incorporated, Natalia GARCIA of Carrollton TX (US) for texas instruments incorporated
IPC Code(s): H04N9/31
CPC Code(s): H04N9/312
Abstract: a controller includes: a processor; and interface circuitry for multiple interfaces. the interface circuitry is coupled to the processor and is configured to: receive load sequences from the processor, the load sequences including a respective load sequence for each of the multiple interfaces, each load sequence including image data intervals and idle intervals; determine a duration for each of the idle intervals; and separately control a sleep mode for each of the multiple interfaces responsive to each of the idle intervals.
Inventor(s): Madhukar Budagavi of Plano TX (US) for texas instruments incorporated, Minhua Zhou of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04N19/82, H04N19/46, H04N19/86
CPC Code(s): H04N19/82
Abstract: a method for adaptive loop filtering of a reconstructed picture in a video encoder is provided that includes determining whether or not sample adaptive offset (sao) filtering is applied to the reconstructed picture, and using adaptive loop filtering with no offset for the reconstructed picture when the sao filtering is determined to be applied to the reconstructed picture.
Inventor(s): Ariton E. Xhafa of Plano TX (US) for texas instruments incorporated, Jianwei Zhou of Allen TX (US) for texas instruments incorporated, Xiaolin Lu of Plano TX (US) for texas instruments incorporated
IPC Code(s): H04W40/24, H04B1/7156, H04L45/02, H04W84/18, H04W84/20
CPC Code(s): H04W40/248
Abstract: a network includes at least one node to communicate with at least one other node via a wireless network protocol. the node includes a network configuration module to periodically switch a current node function of the node between an intermediate node function and a leaf node function. the switch of the current node function enables automatic reconfiguration of the wireless network based on detected communications between the at least one node and at least one intermediate node or at least one leaf node via the wireless network protocol.
Inventor(s): Haowen Bu of Wylie TX (US) for texas instruments incorporated, Roger C. McDermott of Wylie TX (US) for texas instruments incorporated, Matthew Richards of Arlington TX (US) for texas instruments incorporated
IPC Code(s): H10B53/30
CPC Code(s): H10B53/30
Abstract: a method forms an integrated circuit, by forming a first conductive member affixed relative to a semiconductor substrate and a second conductive member affixed relative to the semiconductor substrate. the method also forms a ferroelectric member between the first and second conductive members. the ferroelectric member has a first portion including a first atomic ratio of lead (pb) relative to other materials in the first portion and a second portion including a second atomic ratio of lead relative to other materials in the second portion, the second atomic ratio differing from the first atomic ratio.
TEXAS INSTRUMENTS INCORPORATED patent applications on October 17th, 2024
- TEXAS INSTRUMENTS INCORPORATED
- G01F1/66
- G01F1/667
- G01F15/061
- H04Q9/00
- CPC G01F1/66
- Texas instruments incorporated
- G01R31/26
- G01R31/3177
- G01R31/3185
- CPC G01R31/2607
- G01R31/317
- G01R31/28
- CPC G01R31/31703
- G06F7/49
- G06F7/501
- G06F17/14
- CPC G06F7/49
- G06F9/38
- G06F9/30
- CPC G06F9/383
- G06F9/46
- G06F9/448
- G06F9/48
- G06F9/54
- G06F11/30
- G06F12/0804
- G06F12/0811
- G06F12/0813
- G06F12/0817
- G06F12/0831
- G06F12/0855
- G06F12/0871
- G06F12/0888
- G06F12/0891
- G06F12/12
- G06F12/121
- G06F13/16
- CPC G06F9/467
- G06F9/50
- CPC G06F9/4812
- G06F12/0808
- G06F12/0815
- G06F12/084
- G06F12/0895
- G06F12/128
- CPC G06F12/0811
- G06F12/10
- G06F13/40
- G06F13/42
- CPC G06F13/1668
- G06T7/269
- G06T3/40
- G06V10/25
- G06V10/50
- G06V20/40
- G06V20/56
- G06V20/64
- CPC G06T7/269
- H01F27/40
- H01F27/06
- H01F27/24
- H01F27/29
- H01F41/04
- CPC H01F27/40
- H01L23/495
- H01L21/56
- H01L23/00
- H01L23/31
- CPC H01L23/49541
- H01L23/498
- H01L21/48
- H05K1/02
- CPC H01L23/49861
- H01L29/36
- H01L21/265
- CPC H01L29/36
- H04L5/00
- H04L1/00
- H04L5/14
- H04W28/02
- H04W72/21
- H04W72/54
- H04W72/542
- H04W76/00
- CPC H04L5/0073
- H04N9/31
- CPC H04N9/312
- H04N19/82
- H04N19/46
- H04N19/86
- CPC H04N19/82
- H04W40/24
- H04B1/7156
- H04L45/02
- H04W84/18
- H04W84/20
- CPC H04W40/248
- H10B53/30
- CPC H10B53/30
