TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on October 17th, 2024
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. on October 17th, 2024
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 99 patent applications
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. has applied for patents in the areas of H01L29/66 (28), H01L29/78 (18), H01L29/06 (18), H01L29/423 (18), H01L21/8234 (16) H01L29/785 (3), H01L25/0657 (3), H10B10/12 (3), H01L21/823842 (2), H01L29/0673 (2)
With keywords such as: layer, structure, semiconductor, gate, dielectric, substrate, region, device, source, and drain in patent application abstracts.
Patent Applications by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Inventor(s): Chien-Hung WANG of Toufen Township (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Chih LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hung LIAO of Sanchong City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Yao LEE of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Wei Chang CHENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B05C11/10, F16K7/12, F16K23/00, F16K31/122, F16K37/00, H01L21/67, B05C5/02, B05C11/08, G03F7/16, G03F7/30
CPC Code(s): B05C11/1002
Abstract: a method of preventing drippage in a liquid dispensing system includes generating at least a first proxy signal representing at least a first indirect measure of a position of a first automatic control valve (acv), wherein the first acv has positions ranging from fully closed to fully open. the method further includes recognizing, based on at least the first proxy signal, whether a failure state exists in which the first acv has failed to close. the method further includes causing a second acv to close when the failure state exists, wherein the second acv is fluidically connected to the first acv, and the second acv has positions ranging from fully closed to fully open.
Inventor(s): Sheng-Mu You of Zhunan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Jen Liu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B24B37/04, C09G1/02, C09K3/14
CPC Code(s): B24B37/044
Abstract: a method of performing a polishing process is provided. the method may include forming spherical titanium dioxide nano-particles, covering the spherical titanium dioxide nano- particles with an organic coating, storing the spherical titanium dioxide nano-particles together with an oxidizer, forming a polishing solution with the spherical titanium dioxide nano-particles, applying the polishing solution on a surface of a work piece, and polishing the surface of the work piece with the polishing solution.
Inventor(s): Yi-Chuan TENG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yin TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hua CHU of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Wen CHENG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): B81B3/00, B81C1/00, H04R19/00, H10N30/30
CPC Code(s): B81B3/001
Abstract: structures and formation methods of a semiconductor device structure are provided. the semiconductor device structure includes a substrate and a dielectric layer formed over the substrate. the semiconductor device structure further includes a movable membrane formed over the dielectric layer. in addition, the movable membrane includes first recessed portions arranged in a ring shape in a top view and second recessed portions surrounded by the first recessed portions.
Inventor(s): Yu Kai CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jen WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Kun FANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ko-Bin KAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01M3/02, G03F7/16, H01L21/67
CPC Code(s): G01M3/02
Abstract: a method of manufacturing a semiconductor device includes moving a nozzle from a standby location to a dispensing location, wherein the nozzle is connected to a liquid supply pipe and is configured to dispense a processing liquid to a surface of a substrate, and an end portion of the liquid supply pipe adjoined to the nozzle is covered with a pipe casing. the method further includes illuminating the end portion of the liquid supply pipe prior to dispensing of the processing liquid. the method further includes determining whether the liquid supply pipe is leaking based on an intensity of refracted from the end portion of the liquid supply pipe.
Inventor(s): Chia-Hsi WANG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Yu CHEN of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Mu CHO of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chung Hsien LIAO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01N21/3504, H01L21/66, H01L21/67
CPC Code(s): G01N21/3504
Abstract: a system for monitoring a precursor tank during a deposition process includes a sensor and a signal processor. the sensor includes a sensor chamber connected in line with the precursor tank and a deposition chamber, a radiation emitter to emit a radiation passing through a precursor-containing gas in the sensor chamber, and a radiation receiver to receive the radiation passed through the precursor-containing gas. the signal processor obtains an absorption spectrum of the precursor-containing gas from the received radiation and determines a remaining precursor amount in the precursor tank based on the absorption spectrum. the system facilitates inline monitoring the remaining precursor amount in the precursor tank during a deposition operation, thereby advantageously reducing risks of undergoing a deposition operation while the remaining precursor amount is unacceptably low and avoiding replacing the precursor tank while the remaining precursor amount is acceptable.
Inventor(s): Jian-Ting Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Han Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Hua Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R1/04, H01R12/70
CPC Code(s): G01R1/0433
Abstract: a testing apparatus for a semiconductor package includes a circuit board, testing patterns and a socket. the circuit board has a testing region and includes a plurality of testing contacts and a plurality of signal contacts distributed in the testing region. the testing patterns are embedded in the circuit board and electrically connected to the testing contacts, where each of the testing patterns includes a first conductive line and a second conductive line including a main portion and a branch portion connected to main portion. the first conductive line is connected to the main portion. the socket is located on the circuit board and comprising connectors electrically connected to the circuit board, wherein the connectors are configured to transmit electric signals for testing the semiconductor package from the testing apparatus.
Inventor(s): Haohua Zhou of Fremont CA (US) for taiwan semiconductor manufacturing company, ltd., Mei Hsu Wong of Saratoga CA (US) for taiwan semiconductor manufacturing company, ltd., Tze-Chiang Huang of Saratoga CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G01R27/16, G01R31/30, G01R31/319
CPC Code(s): G01R27/16
Abstract: systems, devices, and methods are described herein for measuring an impedance of a dut using an integrated impedance measurement device. a system includes a plurality of measurement circuits, a fft processor, and a controller. the measurement circuits are coupled to the duts. each measurement circuit is configured to generate a clock signal for a respective dut, detect a voltage of the respective dut, and generate first voltage related data using the clock signal and the voltage. the fft processor is coupled to the measurement circuits. the fft processor is configured to convert the first voltage related data into second voltage related data using a fast fourier transform for each measurement circuit. the controller is coupled to the measurement circuits and the fft processor. the controller is configured to calculate an impedance using the second voltage related data for each measurement circuit and output the impedance to each dut.
Inventor(s): Wei-Kang Liu of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hau-Yan Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yingkit Felix Tsui of Cupertino CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/125, G02B6/134
CPC Code(s): G02B6/125
Abstract: various embodiments of the present disclosure are directed towards a photonic device including a temperature adjustment element. a first waveguide overlies an insulating layer. a second waveguide overlies the insulating layer. the temperature adjustment element includes a heater structure aligned with a segment of the first waveguide and a cooler structure aligned with a segment of the second waveguide. the heater structure is configured to increase a temperature of the segment of the first waveguide to a first temperature. the cooler structure is configured to reduce a temperature of the segment of the second waveguide to a second temperature less than the first temperature.
Inventor(s): Chan-Hong CHERN of Palo Alto CA (US) for taiwan semiconductor manufacturing company, ltd., Min-Hsiang HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02B6/136, G02B6/12, G02B6/122
CPC Code(s): G02B6/136
Abstract: a photonic structure is provided. the photonic structure includes an oxide structure surrounded by a semiconductor substrate, a buried oxide layer over the semiconductor substrate, and an optical coupling region over the buried oxide layer. the oxide structure has a first side surface and a second side surface opposite to the first side surface. in a plan view, the optical coupling region is tapered from the first side surface of the oxide structure to the second side surface of the oxide structure.
Inventor(s): Yu-Hao CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hui Yu LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Feng KUAN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Te WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G02F1/01, H10N10/01, H10N10/17, H10N10/80, H10N10/852, H10N10/855
CPC Code(s): G02F1/0147
Abstract: a method includes forming, over a substrate, an optical component and first, second and third thermal control mechanisms. the optical component includes first and second main paths, and first and second side paths each having opposite ends correspondingly coupled to the first and second main paths. the second side path is spaced from the first side path. each of the first, second and third thermal control mechanisms includes a first thermoelectric member having a first conductivity type, a second thermoelectric member having a second conductivity type opposite to the first conductivity type, and a conductive structure that electrically connects the first thermoelectric member to the second thermoelectric member. the first side path is between the first and third thermal control mechanisms. the second side path is between the second and third thermal control mechanisms. the third thermal control mechanism is between the first and second side paths.
Inventor(s): Pei-Cheng HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Chang LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Huan-Ling LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/64
CPC Code(s): G03F1/64
Abstract: a pellicle for an euv photo mask includes a membrane attached to a frame. the membrane includes nanotubes, ru—o—x catalyst structures partially covering a surface of each nanotube, and a protection layer to cover the ru—o—x catalyst structures and the surface of each nanotube. x is a metal element of mo, ti, zr or nb. the ru—o—x catalyst structures include first nano-particles of a x-containing material formed on the surface of each nanotube, and second nano-particles of a ru-containing material formed on the first nano-particles, thereby forming catalysts or catalyst bridges. the pellicle advantageously has high euv light transmittance and improved endurance against attacking particles (such as hydrogen particles), thereby having prolonged lifetime.
Inventor(s): Hsin-Chang Lee of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Pei-Cheng Hsu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ta-Cheng Lien of Cyonglin Township (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsai-Sheng Gau of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hsiang Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F1/64, H01L21/033
CPC Code(s): G03F1/64
Abstract: a method for preparing a pellicle assembly includes reducing the thickness of one or more initial membrane(s) to obtain a pellicle membrane. the pellicle membrane is then affixed to a mounting frame to obtain the pellicle assembly. compressive pressure can be applied to reduce the thickness of the initial membrane(s). alternatively, the thickness can be reduced by stretching the initial membrane(s) to obtain an extended membrane. a mounting frame is then affixed to a portion of the extended membrane. the mounting frame and the portion of the extended membrane are then separated from the remainder of the extended membrane to obtain the pellicle assembly. the resulting pellicle assemblies include a pellicle membrane that is attached to a mounting frame. the pellicle membrane can be formed from nanotubes and has a combination of high transmittance, low deflection, and small pore size.
Inventor(s): Ching-Yu CHANG of Yilang County (TW) for taiwan semiconductor manufacturing company, ltd., An-Ren ZI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yuan Chih LO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Cheng WANG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/38, G03F7/004, H01L21/027, H01L21/311, H01L21/3213
CPC Code(s): G03F7/38
Abstract: a method includes the following steps. a target layer is formed on a substrate. a resist layer is formed on the target layer. the resist layer is exposed such that secondary electrons are produced in the resist layer. the secondary electrons are terminated using an additive. the resist layer is developed. the target layer is etched using the developed resist layer as a mask.
Inventor(s): Yu-Huan CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hsuan WU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hsun TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Chieh CHIEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Jui CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G03F7/00, H05G2/00
CPC Code(s): G03F7/70858
Abstract: a photolithographic apparatus includes a droplet generator, a droplet generator maintenance system, and a controller communicating with the droplet generator maintenance system. the droplet generator maintenance system operatively communicates with the droplet generator, a coolant distribution unit, a gas supply unit, and a supporting member. the gas supply unit includes a heat exchange assembly and an air heating assembly. the coolant distribution unit is configured to control the temperature of the droplet generator within the acceptable droplet generator range.
Inventor(s): Mohammad AL-SHYOUKH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Alex KALNITSKY of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G05F3/20, G05F3/26
CPC Code(s): G05F3/20
Abstract: a voltage reference includes a pmos transistor including a gate and drain coupled to an input and a source coupled to a voltage node through a resistor, three pmos transistors including gates coupled to the input and sources coupled to the voltage node through resistors, an n-type flipped-gate transistor including a gate and drain coupled to a pmos transistor drain and a source coupled to a negative supply node, an nmos transistor including a gate coupled to the n-type flipped-gate transistor gate, a drain coupled to a pmos transistor drain, and a source coupled to an output, an nmos transistor including a gate coupled to a pmos transistor drain, a drain coupled to the output, and a source coupled to the negative supply node through a resistor, and an nmos transistor including a drain coupled to the output and a gate and source coupled to the negative supply node.
Inventor(s): Neil EVERETTE of Austin TX (US) for taiwan semiconductor manufacturing company, ltd., Willow LAFONE of Durham NC (US) for taiwan semiconductor manufacturing company, ltd., Danielle JUSTILIEN of Morrisville NC (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F9/451, G06F3/04847, G06F8/38, G06F40/109
CPC Code(s): G06F9/451
Abstract: some implementations described herein provide apparatuses and techniques related to graphical user interface design conformance and useability. the apparatuses and techniques include a graphical user interface design management server including a graphical user interface design conformance and a measure of useability application. the graphical user interface design management server may receive one or more attribute changes related to a design of a graphical user interface. the graphical user interface design management server may then access a storage device containing graphical user interface design rules and determine a degree of conformance of a graphical user interface generated using the attribute changes to the graphical user interface design rules. further, and using machine learning techniques, the graphical user interface design management server may determine one or more additional changes to the attributes that improve the measure of useability of the graphical user interface for anticipated users of the graphical user interface.
Inventor(s): Jaw-Juinn Horng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Chin Tsao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/33, G06F30/327
CPC Code(s): G06F30/33
Abstract: an integrated circuit includes a core domain having at least one core domain design rule limitation of a smaller device and a lower operating voltage, an input/output domain having at least one input/output domain design rule limitation of a larger device than the smaller device of the core domain and a higher operating voltage than the lower operating voltage of the core domain, and a mapping cell that includes two or more electrical devices that each meet the at least one core domain design rule limitation. the mapping cell is configured to be an input/output device and operate in the input/output domain at the higher operating voltage of the input/output domain.
Inventor(s): Chun-Yen Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Bao-Ru Young of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Heng Hsieh of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/392, H01L27/088, H01L29/78
CPC Code(s): G06F30/392
Abstract: in some embodiments, the present disclosure relates to an integrated chip. the integrated chip includes a fin of semiconductor material protruding outward from an upper surface of a substrate. a doped region is arranged within the fin of semiconductor material and laterally between a first region and a second region of the fin of semiconductor material. a first gate structure is over the first region of the fin of semiconductor material, a second gate structure is over the second region of the fin of semiconductor material, and a third gate structure is over the doped region. source/drain regions are between the first gate structure, the second gate structure, and the third gate structure.
Inventor(s): Chia-Chun LIAO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shuang DAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yawen CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Meng-Hsuan WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G06F30/398
CPC Code(s): G06F30/398
Abstract: a method of performing a design rule check includes clustering at least one of a plurality of rules with overlapping operations from a plurality of operations or the plurality of operations with overlapping rules from the plurality of rules. the method further includes at least one of transforming at least one of the clustered plurality of operations into a first operation group or a second operation group, or transforming at least one of the clustered plurality of rules into a first rule group or a second rule group. the method even further includes at least one of assigning at least one of the first operation group to a first processor or the second operation group to a second processor, or assigning at least one of the first rule group to the first processor or the second rule group to the second processor.
Inventor(s): Chia-Fu Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hon-Jarn Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hao Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ku-Feng Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Chun Shih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Der Chih of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/16, H10B61/00, H10N50/10
CPC Code(s): G11C11/1675
Abstract: a reference circuit for generating a reference current includes a plurality of resistive elements including at least one magnetic tunnel junction (mtj). a control circuit is coupled to a first terminal of the at least one mtj and is configured to selectively flow current through the at least one mtj in the forward and inverse direction to generate a reference current.
Inventor(s): Yen-An Chang of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Lin Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Fu Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): G11C11/4091, G06F7/523, G11C11/4094, G11C11/4096
CPC Code(s): G11C11/4091
Abstract: a memory device for cim has a memory array including a plurality of memory cells arranged in an array of rows and columns. the memory cells have a first group of memory cells and a second group of memory cells. each row of the array has a corresponding word line, with each memory cell of a row of the array coupled to the corresponding word line. each column of the array has a corresponding bit line, with each memory cell of a column of the array coupled to the corresponding bit line. a control circuit is configured to select the first group of memory cells or the second group of memory cells in response to a group enable signal.
Inventor(s): Yen-Liang LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Kang HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chuan TAI of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01J37/34, C23C14/18, C23C14/35, C23C14/54, H01J37/32
CPC Code(s): H01J37/345
Abstract: some implementations described herein provide a physical vapor deposition tool. the physical vapor deposition tool includes a magnet component, a single cathode, and a power circuit for biasing a pedestal that supports a semiconductor substrate. during a deposition operation that deposits an inert metal material, the physical vapor deposition tool may modulate an electromagnetic field emanating from the magnet component that includes spiral-shaped bands having different ranges of magnetic strength. the physical vapor deposition tool may have an increased throughput relative to a physical vapor deposition tool without the magnet component, the single cathode, and the power circuit. additionally, or alternatively, the inert metal material may have a grain size that is greater relative to a grain size of an inert metal material deposited using the physical vapor deposition tool without the magnet component, the single cathode, and the power circuit.
Inventor(s): Shu-Jui CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Yuan WANG of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Che HUANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Hsin CHIEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chenming HU of Oakland CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/20, H01L21/02, H01L21/768, H01L29/417, H01L29/51
CPC Code(s): H01L21/20
Abstract: an epitaxial structure includes a substrate and a dielectric layer. the dielectric layer is on the substrate. the substrate comprises a single crystal metal or a single crystal 2d material. the dielectric layer is in physical contact with the substrate. the dielectric layer comprises a non-perovskite structure with defined grain orientation with ferroelectric (fe) phase or antiferroelectric (afe) phase.
Inventor(s): Chun-Jung HUANG of Tuku Township (TW) for taiwan semiconductor manufacturing company, ltd., Li-Hsin CHU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Feng TSAI of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Henry PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuang Huan HSU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung Wei CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Lin HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/265, C23C14/48, C23C14/54, H01L21/66
CPC Code(s): H01L21/26586
Abstract: the present disclosure describes a system and a method for an ion implantation (imp) process. the system includes an ion implanter configured to scan an ion beam over a target for a range of angles, a tilting mechanism configured to support and tilt the target, an ion-collecting device configured to collect a distribution and a number of ejected ions from the ion beam scan over the target, and a control unit configured to adjust a tilt angle based on a correction angle determined based on the distribution and number of ejected ions.
Inventor(s): Sung-Li Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Yi Huang of Hsin-chu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Yun Peng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Mrunal A. Khaderbad of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hung Chu of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shuen-Shin Liang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Keng-Chu Lin of Ping-Tung (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/265, H01L21/768, H01L23/532, H01L23/535
CPC Code(s): H01L21/26586
Abstract: a method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. the method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. the method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. after the annealing, the method further includes performing a chemical mechanical planarization (cmp) process to remove at least a portion of the first metal.
Inventor(s): Han-Yu Lin of Nantou County (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ruei Jhan of Keelung City (TW) for taiwan semiconductor manufacturing company, ltd., Fang-Wei Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Li-Te Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Pinyen Lin of Rochester NY (US) for taiwan semiconductor manufacturing company, ltd., Tze-Chung Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/311, C23C16/452, H01L21/67, H01L21/677
CPC Code(s): H01L21/311
Abstract: a semiconductor fabrication apparatus includes a processing chamber for etching, a substrate stage integrated in the processing chamber and being configured to secure a semiconductor wafer, and a gas distribution plate integrated inside the processing chamber. the processing chamber includes a sidewall and a top surface. the semiconductor fabrication apparatus further includes a heating mechanism disposed on the sidewall of the processing chamber and is operable to perform a baking process to remove a by-product generated during the etching, and a reflective mirror configured inside the processing chamber to reflect thermal energy from the heating mechanism toward the semiconductor wafer, the reflective mirror being located on the top surface of the processing chamber. the gas distribution plate defines a portion of the top surface of the processing chamber. from a top view, a portion of the reflective mirror is disposed between the heating mechanism and the gas distribution plate.
Inventor(s): Shahaji B. MORE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chandrashekhar Prakash SAVANT of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/3213, H01L21/28, H01L21/8234, H01L27/092
CPC Code(s): H01L21/32139
Abstract: a semiconductor device includes a substrate; first and second fin structures extending above the substrate; a metal layer on the first and second fin structures; an isolation structure extending through the metal layer between the first and second fin structures, the isolation structure being configured to electrically isolate a first portion of the metal layer on the first fin structure from a second portion of the metal layer on the second fin structure, and the isolation structure having substantially vertical sidewalls; and a passivation layer between at least an upper portion of the isolation structure and an adjacent portion of the metal layer, the passivation layer extending laterally into the metal layer.
Inventor(s): Hsin-Hao YEH of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, H01L21/225, H01L21/268, H01L21/324, H01L21/66, H01L21/68, H01L23/544
CPC Code(s): H01L21/67115
Abstract: a method for using a system for annealing a wafer is provided. the method includes generating a laser beam by a laser beam generator. the method also includes projecting the laser beam with a first laser parameter onto a first semiconductor die of the wafer along at least one annealing orbit by a controller. arranging a first annealing orbit to cover a source/drain region of a first transistor of the first semiconductor die and a second annealing orbit to cover a source/drain region of the first transistor of the first semiconductor die by the controller. a first gate electrode of the first transistor of the first semiconductor die is between and separated from the first annealing orbit and the second annealing orbit.
Inventor(s): Hsien Yu TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Feng LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/67, G06F30/367, G06F30/398, G06F119/08
CPC Code(s): H01L21/67248
Abstract: a system for evaluating a heat sensitive structure of an integrated circuit design including a memory for retrieving and storing integrated circuit design layout data, thermal data, process data, and one or more operational parameters, a processor capable of accessing the memory and identifying a target region having a nominal temperature t, a plurality of heat generating structures and/or heat dissipating structures having corresponding impact areas that encompass a portion of the target region, calculating the temperature increases and/or decreases in the target region as a result of thermal coupling between the target region and the heat generating structures and/or heat dissipating structures, and conducting one or more parametric evaluations of the target region at an adjusted evaluation temperature tafter which a network interface transmits the result(s) of the parametric evaluation(s) for use in a design review.
Inventor(s): Sung-Ju Huang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Wei Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung Wu of Zhunan (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Fam Shiu of Toufen (TW) for taiwan semiconductor manufacturing company, ltd., Chyi-Tsong Ni of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/677, H01L21/673
CPC Code(s): H01L21/67742
Abstract: the present disclosure relates to systems and methods for reducing the humidity within a foup (front opening unified pod) when loaded on an efem (equipment front end module) for transfer of a semiconductor wafer substrate during fabrication processes. a deflector of specified structure is placed inside the efem above the load port of the foup. the deflector directs airflow in the efem away from the load port. the deflector includes a body with a plurality of apertures in the deflector body, and with a sloped front surface. thus, the degree of penetration of high-humidity air from the efem into the foup is reduced.
Inventor(s): Yu-Hung Cheng of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Pu-Fang Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Ta Wu of Shueishang Township (TW) for taiwan semiconductor manufacturing company, ltd., Po-Jung Chiang of Zhongli City (TW) for taiwan semiconductor manufacturing company, ltd., Ru-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Victor Y. Lu of Foster City CA (US) for taiwan semiconductor manufacturing company, ltd., Yen-Hsiu Chen of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yeur-Luen Tu of Taichung (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Lung Yeh of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Chieh Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/762, H01L21/02, H01L21/265, H01L21/324, H01L21/84
CPC Code(s): H01L21/76254
Abstract: various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (soi) device with an impurity competing layer to absorb potential contamination metal particles during an annealing process, and the soi structure thereof. in some embodiments, an impurity competing layer is formed on the dummy substrate. an insulation layer is formed over a support substrate. a front side of the dummy wafer is bonded to the insulation layer. an annealing process is performed and the impurity competing layer absorbs metal from an upper portion of the dummy substrate. then, a majority portion of the dummy substrate is removed including the impurity competing layer, leaving a device layer of the dummy substrate on the insulation layer.
Inventor(s): Hsin-Yen HUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Ya LO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Kuan LEE of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin TENG of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin SHUE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang CHANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L23/532, H01L29/06, H01L29/423, H01L29/78, H01L29/786
CPC Code(s): H01L21/7682
Abstract: a semiconductor device structure and method for forming the same are provided. the semiconductor device structure includes a first conductive layer formed over a substrate, and an air gap structure adjacent to the first conductive layer. the semiconductor device structure includes a support layer formed over the air gap structure, and a sidewall surface of the support layer is aligned with a sidewall surface of the air gap structure.
Inventor(s): Ru-Gun Liu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Ming Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hoi-Tou Ng of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/768, H01L21/027, H01L21/311, H01L23/522
CPC Code(s): H01L21/76897
Abstract: the present disclosure provides a semiconductor structure. the semiconductor structure includes a substrate, a first conductive feature positioned in a top portion of the substrate, a dielectric layer over the substrate, and a second conductive feature surrounded by the dielectric layer and in contact with the first conductive feature. the first conductive feature includes a metal layer and a reflective layer on the metal layer. the metal layer and the reflective layer have a same width. the reflective layer has a reflectivity higher than the metal layer.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao Wen Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088
CPC Code(s): H01L21/823456
Abstract: a semiconductor device may be formed by forming a first fin and a second fin in a first area and a second area of a substrate, respectively; which may be followed by forming of a first dummy gate structure and a second dummy gate structure straddling the first fin and second fin, respectively and forming a sacrificial layer extending along a bottom portion of the second dummy gate structure. the first dummy gate structure may be replaced with a first metal gate structure, while the second dummy gate structure and the sacrificial layer may be replaced with a second metal gate structure.
Inventor(s): Kuo-Sheng CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., You-Hua CHOU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yusuke ONIKI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/02, H01L21/8238, H01L27/088, H01L27/092
CPC Code(s): H01L21/823462
Abstract: a semiconductor device includes a fin structure. the semiconductor device further includes a gate structure over a region of the fin structure, wherein a bottom-most surface of the gate structure is offset from a top-most surface of the fin structure beyond the region of the fin structure. the semiconductor device further includes a channel layer between the fin structure and the gate structure, wherein the channel layer extends above the top-most surface of the first fin structure beyond the region of the fin structure.
Inventor(s): Huan-Chieh SU of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd., Li-Zhen YU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yuan CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Lo-Heng CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi CHUANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/78, H01L29/786
CPC Code(s): H01L21/823481
Abstract: semiconductor devices and methods of forming the same are provided. a semiconductor device according to the present disclosure includes first channel members over a first backside dielectric feature, second channel members over a second backside dielectric feature, a first epitaxial feature abutting the first channel members and over the first backside dielectric feature, a second epitaxial feature abutting the second channel members and over the second backside dielectric feature, a first gate structure wrapping around each of the first channel members, a second gate structure wrapping around each of the second channel members, and an isolation feature laterally stacked between the first backside dielectric feature and the second backside dielectric feature. a bottommost portion of the isolation feature is below bottom surfaces of the first and second gate structures, and a topmost portion of the isolation feature is above top surfaces of the first and second gate structures.
Inventor(s): Joanna Chaw Yane Yin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsi Wu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chiang Ting of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuang-Hsin Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8234, H01L21/762, H01L21/8238, H01L21/84, H01L27/088, H01L27/092, H01L29/66
CPC Code(s): H01L21/823481
Abstract: in an embodiment, a device includes a first active region over a substrate, a portion of the first active region having a first surface, the first surface defining a channel and being a first distance from the substrate. a dummy structure is adjacent to the first active region and has a sidewall extending from the substrate to a second surface facing way from the substrate, the second surface being a second distance, less than the first distance, from the substrate. an isolation region extends from a sidewall of a lower portion of the first active region over the second surface of the dummy semiconductor structure.
Inventor(s): Guan-Lin Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei Tsai of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Shi Ning Ju of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jui-Chien Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng Chiang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/28, H01L27/092, H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L21/823828
Abstract: self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. an exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. the channel layer extends along a first direction between the source/drain features. a first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. the channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. the metal gate is disposed between the channel layer and the second dielectric fin. in some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. the first isolation feature and the second isolation feature are configured differently.
Inventor(s): Hsin-Yi Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/285, H01L27/092, H01L29/49
CPC Code(s): H01L21/823842
Abstract: a method includes depositing a first conductive layer over a gate dielectric layer; depositing a first work function tuning layer over the first conductive layer; selectively removing the first work function tuning layer from over a first region of the first conductive layer; doping the first work function tuning layer with a dopant; and after doping the first work function tuning layer performing a first treatment process to etch the first region of the first conductive layer and a second region of the first work function tuning layer. the first treatment process etches the first conductive layer at a greater rate than the first work function tuning layer.
Inventor(s): Chung-Liang CHENG of Changhua County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/8238, H01L21/02, H01L21/28, H01L27/092, H01L29/06, H01L29/423, H01L29/49, H01L29/66, H01L29/786
CPC Code(s): H01L21/823842
Abstract: a semiconductor device with different configurations of gate structures and a method of fabricating the semiconductor device are disclosed. the semiconductor device includes first and second gate structures disposed on first and second nanostructured channel regions, respectively. the first gate structure includes a nwfm layer disposed on the first nanostructured channel region, a barrier layer disposed on the nwfm layer, a first pwfm layer disposed on the barrier layer, and a first gate fill layer disposed on the first pwfm layer. sidewalls of the first gate fill layer are in physical contact with the barrier layer. the second gate structure includes a gate dielectric layer disposed on the second nanostructured channel region, a second pwfm layer disposed on the gate dielectric layer, and a second gate fill layer disposed on the pwfm layer. sidewalls of the second gate fill layer are in physical contact with the gate dielectric layer.
Inventor(s): Ming-Sung Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Kuo Hsiao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Cheng Chen of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66
CPC Code(s): H01L22/12
Abstract: a measurement pattern for monitoring overlay shift of bonded wafers includes a top wafer pattern and a bottom wafer pattern. the top wafer pattern includes a first portion with a width wx1 measured along a first axis. the bottom wafer pattern includes a first part with a width wx2 measured along the first axis, wherein the first portion of the top wafer pattern and the first part of the bottom wafer pattern are separated by a target distance dx, and wherein the measurement pattern satisfies the following measurement formulas:
Inventor(s): Ming-Sung Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsun-Kuo Hsiao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Cheng Chen of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Po-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L21/66
CPC Code(s): H01L22/12
Abstract:
Inventor(s): Po-Chen LAI of Hsinchu county (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chih YEW of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/31, H01L21/56, H01L23/00, H01L23/14, H01L23/29, H01L23/498, H01L25/065
CPC Code(s): H01L23/3185
Abstract: structures and formation methods of a chip package structure are provided. the method includes mounting semiconductor dies over die regions of an interposer substrate. the adjacent die regions are separated from one another by a gap region of the interposer substrate. the method also includes forming first underfill material layers and a second gap-filling layer over the interposer substrate corresponding to the gap region. the method further includes forming an encapsulating layer over the interposer substrate to surround the semiconductor dies, the first underfill material layers, and the second underfill material layer. the gap region has ends and the first underfill material layers is formed adjacent to the ends of the gap region. the young's modulus of the second underfill material layer is less than that of the first underfill material layers.
Inventor(s): Shu-Shen YEH of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Che-Chia YANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Sheng LIN of Zhubei (TW) for taiwan semiconductor manufacturing company, ltd., Chin-Hua WANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao LIN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L21/56, H01L23/00, H01L23/04, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H01L23/3675
Abstract: a chip package structure is provided. the chip package structure includes a wiring substrate. the chip package structure includes a first chip structure over the wiring substrate. the chip package structure includes a heat-spreading lid over the wiring substrate and covering the first chip structure. the heat-spreading lid includes a ring structure and a top plate, the ring structure surrounds the first chip structure, the top plate covers the ring structure and the first chip structure, and the first chip structure has a first sidewall and a second sidewall opposite to the first sidewall.
Inventor(s): Hsin-Yen Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shao-Kuan Lee of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shau-Lin Shue of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao-Kang Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cherng-Shiaw Tsai of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/367, H01L21/48, H01L23/373, H01L23/48, H01L23/522
CPC Code(s): H01L23/3677
Abstract: various embodiments of the present disclosure are directed towards an integrated chip including a device layer including a first surface opposite a second surface. a first thermal dispersion layer overlies the device layer. a second thermal dispersion layer underlies the device layer. a first thermal conductivity of the first thermal dispersion layer is different from a second thermal conductivity of the second thermal dispersion layer.
Inventor(s): Shin-Puu JENG of Po-Shan Village (TW) for taiwan semiconductor manufacturing company, ltd., Po-Hao TSAI of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Yao CHUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng HSU of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Shuo-Mao CHEN of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Techi WONG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/498, H01L21/48, H01L21/52, H01L21/56, H01L21/683, H01L23/00, H01L23/053, H01L23/31, H01L25/00, H01L25/10
CPC Code(s): H01L23/49838
Abstract: a chip package is provided. the chip package includes a substrate structure including: a redistribution structure having a conductive pad; and an insulating layer under the redistribution structure. the chip package includes a first chip over the redistribution structure. the chip package includes a second chip under the substrate structure. a top portion of the second chip extends into the insulating layer from a bottom surface of the insulating layer, the bottom surface faces away from the first chip, and a portion of the insulating layer is between the second chip and the redistribution structure. the chip package includes a first molding layer over the redistribution structure and the first chip. a first sidewall of the first molding layer and a second sidewall of the redistribution structure are substantially level with each other.
Inventor(s): Jie Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/522, H01L23/00, H01L23/31, H01L25/065
CPC Code(s): H01L23/5227
Abstract: a method of forming a semiconductor package includes the following steps. a first die is provided, wherein the first die comprises a plurality of first conductive patterns. a plurality of second conductive patterns are formed over the first die, wherein the second conductive patterns are connected to the first conductive patterns to form a first coil and a second coil surrounding the first coil.
Inventor(s): Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Tsung Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Chuan You of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tien-Lu Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/532, H01L21/768, H01L23/522, H01L29/40, H01L29/417, H01L29/78
CPC Code(s): H01L23/53295
Abstract: semiconductor device and the manufacturing method thereof are disclosed herein. an exemplary semiconductor device comprises a fin disposed over a substrate, a gate structure disposed over a channel region of the fin, such that the gate structure traverses source/drain regions of the fin, a device-level interlayer dielectric (ild) layer of a multi-layer interconnect structure disposed over the substrate, wherein the device-level ild layer includes a first dielectric layer, a second dielectric layer disposed over the first dielectric layer, and a third dielectric layer disposed over the second dielectric layer, wherein a material of the third dielectric layer is different than a material of the second dielectric layer and a material of the first dielectric layer. the semiconductor device further comprises a gate contact to the gate structure disposed in the device-level ild layer and a source/drain contact to the source/drain regions disposed in the device-level ild layer.
Inventor(s): Shih-Ting Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Hsi Wu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Hua Yu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Szu-Wei Lu of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/538, H01L21/48, H01L21/56, H01L21/683, H01L23/00, H01L23/31
CPC Code(s): H01L23/5389
Abstract: a package structure includes a plurality of semiconductor dies, an insulating encapsulant, a redistribution layer and a plurality of connecting elements. the insulating encapsulant is encapsulating the plurality of semiconductor dies. the redistribution layer is disposed on the insulating encapsulant in a build-up direction and electrically connected to the plurality of semiconductor dies, wherein the redistribution layer includes a plurality of conductive lines, a plurality of conductive vias and a plurality of dielectric layers alternately stacked, and a lateral dimension of the plurality of conductive vias increases along the build-up direction. the connecting elements are disposed in between the redistribution layer and the semiconductor dies, wherein the connecting elements includes a body portion joined with the semiconductor dies and a via portion joined with the redistribution layer, wherein a lateral dimension of the via portion decreases along the build-up direction.
Inventor(s): Tao-Yi Hung of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Jam-Wem Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Ji Chen of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wun-Jie Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/60, H01L27/02, H02H9/04
CPC Code(s): H01L23/60
Abstract: a semiconductor device includes a device wafer including a first side and a second side opposite to each other, and a carrier wafer disposed over the first side of the device wafer. the carrier wafer includes an electrostatic discharge (esd) protection circuit. the esd protection circuit includes a first diode and a second diode. the first diode is operatively coupled to a first power rail, and the second diode is operatively coupled to a second power rail at least through the device wafer.
Inventor(s): Chih-Fan HUANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Mao-Nan WANG of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hui-Chi CHEN of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Dian-Hau CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming CHEN of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00
CPC Code(s): H01L24/05
Abstract: a chip structure is provided. the chip structure includes a semiconductor substrate. the chip structure includes a first conductive layer over the first dielectric layer. the chip structure includes a conductive via passing through the first conductive layer and electrically connected to the first conductive layer. the chip structure includes a conductive pad over and in direct contact with the conductive via. the chip structure includes a second conductive layer over and spaced apart from the first conductive layer. the chip structure includes a first dielectric layer conformally covering a second lower portion of a sidewall of the second conductive layer. the chip structure includes a third conductive layer over the first dielectric layer.
20240347489. MEMORY DEVICES_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/00, H01L25/00, H01L25/065, H01L25/18
CPC Code(s): H01L24/08
Abstract: a device includes stacking structures, first conductive contacts, first drivers and second conductive contacts. each of the stacking structures includes alternately stacked first conductive lines and first dielectric layers, and the stacking structures are shaped into first staircase structures and second staircase structures at first and second sides, respectively. the first conductive contacts are bonded to the first conductive lines respectively. the second conductive contacts are bonded to the first drivers respectively, wherein the first conductive contacts and the second conductive contacts are bonded and disposed between the first conductive lines and the first drivers.
Inventor(s): Yi-Hsiu Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ebin Liao of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd., Hong-Ye Shih of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih Chiou of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Jia-Ling Ko of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/56, H01L21/822, H01L23/31, H01L23/544, H01L25/00
CPC Code(s): H01L25/0652
Abstract: the disclosure provides a method of forming a package structure, and the method includes the following steps. a plurality of semiconductor components is bonded to a substrate. a grinding process is performed to thin the plurality of semiconductor components. the plurality of semiconductor components have a first total thickness variation (ttv) after performing the grinding process. a dielectric layer is formed on the substrate. a first chemical mechanical polishing (cmp) is performed to remove a first portion of the dielectric layer on top surfaces of the plurality of semiconductor components; and performing a second cmp process to remove a second portion of the dielectric layer between the plurality of semiconductor components and a portion of the plurality of semiconductor components. after performing the second cmp process, the plurality of semiconductor components has a second ttv less than the first ttv.
20240347512. PACKAGE_simplified_abstract_(taiwan semiconductor manufacturing company, ltd.)
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wen Shih of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hsien-Wei Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L21/304, H01L21/56, H01L21/683, H01L23/00, H01L23/31, H01L23/538, H01L23/544, H01L27/12
CPC Code(s): H01L25/0657
Abstract: a package includes a carrier substrate, a first die, and a second die. the first die and the second die are stacked on the carrier substrate in sequential order. the first die includes a first bonding layer, a second bonding layer, and an alignment mark embedded in the first bonding layer. the second die includes a third bonding layer. a surface of the first bonding layer form a rear surface of the first die and a surface of the second bonding layer form an active surface of the first die. the rear surface of the first die is in physical contact with the carrier substrate. the active surface of the first die is in physical contact with the third bonding layer of the second die.
Inventor(s): Stefan Rusu of Sunnyvale CA (US) for taiwan semiconductor manufacturing company, ltd., Mohammed Rabiul Islam of Austin TX (US) for taiwan semiconductor manufacturing company, ltd., Eric Soenen of Austin TX (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/00, H01L25/00
CPC Code(s): H01L25/0657
Abstract: a three-dimensional integrated circuit (3d ic) package is provided. the 3d ic package includes: a cache die including a low-dropout (ldo) regulator and a cache memory device; a compute die above the cache die, the compute die including a processor; and one or more first interconnect structures connecting the cache die and the compute die in a vertical direction.
Inventor(s): Ming-Fa Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Feng Yeh of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tzuan-Horng Liu of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Wen Shih of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L25/065, H01L23/31, H01L23/522, H01L23/528, H01L23/538, H01L25/00, H01L21/56, H01L23/00, H01L23/29
CPC Code(s): H01L25/0657
Abstract: a chip structure includes first and second semiconductor chips. the first semiconductor chip includes a first semiconductor substrate, a first interconnection layer located on the first semiconductor substrate, a first protection layer covering the first interconnection layer, a gap fill layer located on the first protection layer, and first conductive vias embedded in the gap fill layer and electrically connected with the first interconnection layer. the second semiconductor chip is embedded within the first semiconductor chip and surrounded by the gap fill layer and the first conductive vias, wherein the second semiconductor chip includes a second semiconductor substrate, a second interconnection layer located on the second semiconductor substrate, a second protection layer located on the second interconnection layer, and second conductive vias embedded in the second protection layer and electrically connected with the second interconnection layer, wherein the second semiconductor substrate is bonded to the first protection layer.
Inventor(s): Po-Lin PENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-Jen YANG of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Jam-Wem LEE of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Wei CHU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/02, H01L23/528, H01L27/07, H01L29/06, H01L29/10, H01L29/861
CPC Code(s): H01L27/0277
Abstract: an electrostatic discharge (esd) protection device having a source region coupled to a first electrical node, a first drain region coupled to a second electrical node different from the first electrical node, and an extended drain region between the source region and the first drain region. the extended drain region includes a number n of electrically floating doped regions and a number m of gate regions coupled to the second electrical node, where n and m are integers greater than 1 and n is equal to m. each electrically floating doped region of the n number of floating doped regions alternates with each gate region of the m number of gate regions.
Inventor(s): Shi Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Cheng CHIANG of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun CHENG of HsinChu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Baoshan Township (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Ting PAN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Zhi-Chang LIN of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/088, H01L21/8234, H01L29/06, H01L29/10, H01L29/66, H01L29/78
CPC Code(s): H01L27/0886
Abstract: a semiconductor structure is provided. the semiconductor structure includes a first substrate fin and a second substrate fin extending in a first direction, a first isolation strip extending in the first direction and spaced apart from the first substrate fin and the second substrate fin, a first source/drain structure on the first substrate fin, and a second source/drain structure on the second substrate fin. the first isolation strip is sandwiched between and in contact with a first sidewall of the first source/drain structure and a first sidewall of the second source/drain structure.
Inventor(s): Hsin-Cheng LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Yi CHENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wang YAO of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chee-Wee LIU of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/02, H01L21/8238, H01L23/528, H01L29/06, H01L29/10, H01L29/417, H01L29/423, H01L29/66, H01L29/775
CPC Code(s): H01L27/092
Abstract: an integrated circuit includes a first transistor and a second transistor. the first transistor includes first semiconductor channel layers, first gate structure, and a first source structure and a first drain structure on opposites sides of the first gate structure. the second transistor includes second semiconductor channel layers, second gate structure, and a second source structure and a second drain structure on opposites sides of the second gate structure. the first source structure of the first transistor is electrically coupled to the second drain structure of the second transistor. a thickness of each of the first semiconductor channel layers is less than a thickness of each of the second semiconductor channel layers, and a bandgap of a material of the first semiconductor channel layers is larger than a bandgap of a material of the second semiconductor channel layers.
Inventor(s): Mrunal Abhijith Khaderbad of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sathaiya Dhanyakumar Mahaveer of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/092, H01L21/8238, H01L29/423, H01L29/76, H01L29/786
CPC Code(s): H01L27/0924
Abstract: according to embodiments of the present disclosure, two-dimensional (2d) materials may be used as nanosheet channels for multi-channel transistors. nanosheet channels made two-dimensional (2d) materials can achieve the same drive current at smaller dimensions and/or fewer number of channels, therefore enable scaling down and/or boost derive current. embodiments of the present disclosure also provide a solution of p-type and n-type balancing in a device without increasing footprint of the device.
Inventor(s): Chih-Yu LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Liang CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wei TSAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shang-Wen CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Chun TIEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/12, H01L21/768, H01L23/48
CPC Code(s): H01L27/124
Abstract: a method of making a semiconductor device includes manufacturing a first bridge pillar; manufacturing a first transistor channel bar and first transistor source/drain electrode, the first transistor s/d electrode electrically connecting to the first bridge pillar; manufacturing a second transistor channel bar and second transistor s/d electrode; manufacturing a first metal electrode, the first bridge pillar connecting the first transistor s/d electrode and first metal electrode; manufacturing a first via connected to the first metal electrode; and manufacturing a first conductive line connected to the first via. the first transistor s/d electrode and the second transistor s/d electrode are spaced apart by a first height, the first metal electrode is separate from the second transistor s/d electrode, the first bridge pillar is separate from the second transistor s/d electrode, and the first bridge pillar has a height in the first direction substantially equal to the first height.
Inventor(s): Hao-Lin Yang of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Chieh Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Cheng Hsu of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Jui Wang of Fengshan City (TW) for taiwan semiconductor manufacturing company, ltd., Chen-Jong Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L27/146, H01L23/522, H01L23/552, H01L25/065
CPC Code(s): H01L27/14643
Abstract: various embodiments of the present disclosure relate to an interstitial stacked-integrated-circuit interface shielding structure. a first integrated circuit (ic) chip includes a first dielectric layer. a second ic chip is bonded to the first ic chip at a bond interface and includes a second dielectric layer directly contacting the first dielectric layer at the bond interface. a first pair of conductive pads are respectively in the first and second dielectric layers and directly contacting at the bond interface. a second pair of conductive pads are respectively in the first and second dielectric layers and directly contacting at the bond interface. a pair of shield structures are respectively in the first and second dielectric layers and directly contact at the bond interface. further, the pair of shield structures separate the first pair of conductive pads from the second pair of conductive pads.
Inventor(s): Chien-Hsien Kuo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hon-Lin Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Han-Yi Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Wen Hsiao of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Alexander Kalnitsky of San Francisco CA (US) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01F17/00, H01F17/04, H01F41/04
CPC Code(s): H01L28/10
Abstract: a manufacturing method of a semiconductor device includes: forming a first dielectric layer on inductor traces, openings of the first dielectric layer exposing the inductor traces; disposing a buffer material on the first dielectric layer and the inductor traces in the openings; sequentially disposing an etch stop material and a ferromagnetic material on the buffer material; removing the ferromagnetic material from over the openings to form a core material layer covering a first area; removing the etch stop and buffer materials from the openings to form an etch stop layer and a buffer layer, where the etch stop and buffer layers cover a second area, the first area is smaller than and within the second area; forming a second dielectric layer on the first dielectric layer to embed the buffer, etch stop, and core material layers; and forming inductor vias extending through the first and second dielectric layers.
Inventor(s): Meng-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Te-Hsin Chiu of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Wei Cheng Wu of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Te-An Chen of Beitun (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01G4/30, H01L21/8234, H01L27/06, H01L27/08
CPC Code(s): H01L28/40
Abstract: a semiconductor device and a manufacturing method thereof are provided. the method includes forming an isolation structure in a substrate to define an isolating region and forming a capacitor structure on an upper surface of the isolation structure and comprising a first semiconductor structure and a second semiconductor structure separated by an insulator pattern. the first semiconductor structure and the second semiconductor structure are formed with upper surfaces aligned with one another.
Inventor(s): Min-Feng Kao of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Dun-Nian Yaung of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsing-Chih Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Jen-Cheng Liu of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L23/48, H01L21/8234, H01L23/00, H01L23/522, H01L23/528, H01L25/00, H01L25/065, H01L27/06
CPC Code(s): H01L28/91
Abstract: some embodiments relate to a method. in the method, semiconductor devices are formed on a frontside of a semiconductor substrate. a trench is formed in a backside of the semiconductor substrate. conductive and insulating layers are alternatingly formed in the trench on the backside of the semiconductor substrate to establish a backside capacitor. a backside interconnect structure is formed on the backside of the semiconductor substrate to couple to capacitor electrodes of the backside capacitor.
Inventor(s): Kuo-Cheng CHIANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Guan-Lin CHEN of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Jung-Chien CHENG of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Shi-Ning JU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao WANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L29/423, H01L29/66, H01L29/786
CPC Code(s): H01L29/0665
Abstract: semiconductor structures and methods for forming the same are provided. the semiconductor structure includes first nanostructures formed over a substrate, and a first gate electrode layer formed on the first nanostructures. the semiconductor structure includes a second gate electrode layer adjacent to the first gate electrode layer, and a protective layer formed over the first gate electrode layer and the second gate electrode layer. the semiconductor structure includes a first dielectric structure between the first gate electrode layer and the second gate electrode layer, and the first dielectric structure penetrates through the protective layer.
Inventor(s): Hong-Chih CHEN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Je-Wei HSU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Huan HSIEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao KUO of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Hsiang SU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Hsun CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Chun WU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L27/092, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. the structure includes a source/drain region disposed over a substrate, a first interlayer dielectric layer surrounding a first portion of the source/drain region, a second interlayer dielectric layer distinct from the first interlayer dielectric layer surrounding a second portion of the source/drain region, a silicide layer disposed on the source/drain region, and a conductive contact disposed over the source/drain region. the conductive contact is disposed in the second interlayer dielectric layer.
Inventor(s): Kuo-Chiang TSAI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jeng-Ya YEH of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Jhon-Jhy LIAW of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Mu-Chi CHIANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/06, H01L21/8234, H01L27/088, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L29/0673
Abstract: a method for forming a semiconductor structure is provided. the method for forming the semiconductor structure includes a first contact plug and a second contact plug through a first dielectric layer, forming a second dielectric layer over the first contact plug, the second contact plug and the first dielectric layer, etching the second dielectric layer to form a first opening exposing the first contact plug, the second contact plug and the first dielectric layer, forming a bottom via portion in the first opening, forming a third dielectric layer over the bottom via portion and the second dielectric layer, etching the third dielectric layer to form a second opening exposing the bottom via portion, and forming a top via portion in the second opening. the top via portion and the bottom via portion form a first via.
Inventor(s): Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Li-Zhen Yu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/08, H01L23/528, H01L29/06, H01L29/78
CPC Code(s): H01L29/0843
Abstract: a semiconductor structure includes a source/drain (s/d) feature; one or more channel semiconductor layers connected to the s/d feature; a gate structure engaging the one or more channel semiconductor layers; a first silicide feature at a frontside of the s/d feature; a second silicide feature at a backside of the s/d feature; and a dielectric liner layer at the backside of the s/d feature, below the second silicide feature, and spaced away from the second silicide feature by a first gap. a backside power rail is included.
Inventor(s): Pei Ying LAI of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Chieh LIN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsueh-Ju CHEN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Da LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Hao HOU of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi On CHUI of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/40, H01L21/02, H01L21/283, H01L21/3115, H01L21/822, H01L21/8234, H01L21/8238, H01L27/092, H01L29/423, H01L29/66
CPC Code(s): H01L29/401
Abstract: dipole engineering techniques are disclosed that incorporate dipole dopant and/or nitrogen into gate dielectrics (e.g., high-k dielectric layers thereof) to realize multi-threshold voltage transistor tuning of transistors. the dipole engineering techniques include (1) forming a dipole dopant source layer over gate dielectrics of some transistors, but not other transistors, (2) forming a mask over gate dielectrics of some transistors, but not other transistors, (3) performing a nitrogen-containing thermal drive-in process, and (4) removing the dipole dopant source layer and the mask after the nitrogen-containing thermal drive-in process. the nitrogen-containing thermal drive-in process diffuses nitrogen and dipole dopant (n-dipole dopant and/or p-dipole dopant) into unmasked gate dielectrics having the dipole dopant source layer formed thereon, nitrogen into unmasked gate dielectrics, and dipole dopant into masked gate dielectrics having the dipole dopant source layer formed thereon. masked gate dielectrics without the dipole dopant source layer formed thereon remain undoped.
Inventor(s): Yi-Cheng Chu of Chiayi City (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hua Huang of Miaoli County (TW) for taiwan semiconductor manufacturing company, ltd., Katherine H. CHIANG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L23/522, H01L29/40, H01L29/66, H01L29/786
CPC Code(s): H01L29/41733
Abstract: a semiconductor device is disclosed. the semiconductor device includes a semiconducting material layer, a gate electrode under the semiconducting material layer, a pair of contact terminals over the semiconducting material layer, and a hydrogen-blocking dielectric layer on the semiconducting material layer. the pair of contact terminals penetrates through the hydrogen-blocking dielectric layer to be in contact with the semiconducting material layer at a contact surface, and the contact surface is substantially coplanar with and levelled with an interface between the hydrogen-blocking dielectric layer and the semiconducting material layer.
Inventor(s): Ding-Kang Shih of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Sung-Li Wang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Pang-Yen Tsai of Hsin-Chu Hsian (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/417, H01L21/02, H01L21/762, H01L21/8238, H01L27/092, H01L29/08, H01L29/165, H01L29/66, H01L29/78
CPC Code(s): H01L29/41791
Abstract: examples of an integrated circuit with an interface between a source/drain feature and a contact and examples of a method for forming the integrated circuit are provided herein. in some examples, a substrate is received having a source/drain feature disposed on the substrate. the source/drain feature includes a first semiconductor element and a second semiconductor element. the first semiconductor element of the source/drain feature is oxidized to produce an oxide of the first semiconductor element on the source/drain feature and a region of the source/drain feature with a greater concentration of the second semiconductor element than a remainder of the source/drain feature. the oxide of the first semiconductor element is removed, and a contact is formed that is electrically coupled to the source/drain feature. in some such embodiments, the first semiconductor element includes silicon and the second semiconductor element includes germanium.
Inventor(s): Ru-Shang Hsiao of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ying Hsin Lu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Ching-Hwanq Su of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Pin Chia Su of Tainan County (TW) for taiwan semiconductor manufacturing company, ltd., Ling-Sung Wang of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L27/088, H01L29/40, H01L29/786
CPC Code(s): H01L29/42376
Abstract: the present disclosure provides a semiconductor structure in accordance with some embodiment. the semiconductor structure includes a semiconductor substrate having a first circuit region and a second circuit region; active regions extended from the semiconductor substrate and surrounded by isolation features; first transistors that include first gate stacks formed on the active regions and disposed in the first circuit region, the first gate stacks having a first gate pitch less than a reference pitch; and second transistors that include second gate stacks formed on the active regions and disposed in the second circuit region, the second gate stacks having a second pitch greater than the reference pitch. the second transistors are high-frequency transistors and the first transistors are logic transistors.
Inventor(s): Shih-Yao Lin of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hsiao Wen Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Han Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/423, H01L21/8234, H01L29/66, H01L29/786
CPC Code(s): H01L29/42392
Abstract: a method for making a semiconductor device includes forming a fin structure that extends along a first direction and comprises a plurality of sacrificial layers and a plurality of channel layers alternately stacked on top of one another, forming a dummy gate structure over the fin structure and extending along a second direction perpendicular to the first direction, and forming a gate spacer. the gate spacer extends in the second direction along respective upper sidewall portions of the dummy gate structure and is separated by a portion of the dummy gate structure from a topmost one of the plurality of channel layers, such that a first distance between a bottom surface of the gate spacer and a top surface of the topmost one of the plurality of channel layers is defined by the portion of the dummy gate structure.
Inventor(s): Yi-Hsiu Liu of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Cheng Yang of Zhudong Township (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Lin Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ming Chen of Chu-Pei City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ting Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/51, H01L21/311, H01L27/088, H01L29/66
CPC Code(s): H01L29/515
Abstract: a semiconductor structure includes a first device and a second device. the first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. the second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. the first air spacer and the second air spacer have different sizes.
Inventor(s): Chi-Wen LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Hsiung WANG of Hsin-Chu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/94
CPC Code(s): H01L29/66181
Abstract: a device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. the device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. the fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. the device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.
Inventor(s): Ming-Ho Lin of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-I Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chun-Heng Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi On Chui of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/3213, H01L29/06, H01L29/78
CPC Code(s): H01L29/66545
Abstract: a method includes forming a protruding structure, and forming a non-conformal film on the protruding structure using an atomic layer deposition (ald) process. the non-conformal film includes a top portion directly over the protruding structure, and a sidewall portion on a sidewall of the protruding structure. the top portion has a first thickness, and the sidewall portion has a second thickness smaller than the first thickness.
Inventor(s): Ting-Gang Chen of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Tai-Chun Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Chang Wen of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Shu-Yuan Ku of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Fu-Kai Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tze-Liang Lee of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yung-Cheng Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yi-Ting Fu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/311, H01L21/762, H01L21/768, H01L21/8238, H01L27/092, H01L29/78
CPC Code(s): H01L29/66545
Abstract: a method includes forming a first and a second dummy gate stack crossing over a semiconductor region, forming an ild to embed the first and the second dummy gate stacks therein, replacing the first and the second dummy gate stacks with a first and a second replacement gate stack, respectively, performing a first etching process to form a first opening. a portion of the first replacement gate stack and a portion of the second replacement gate stack are removed. the method further includes filling the first opening to form a dielectric isolation region, performing a second etching process to form a second opening, with the ild being etched, and the dielectric isolation region being exposed to the second opening, forming a contact spacer in the second opening, and filling a contact plug in the second opening. the contact plug is between opposite portions of the contact spacer.
Inventor(s): Jin-Mu Yin of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Wei-Yang Lee of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Hao Yu of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Ting Chen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Pin Lin of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L29/423, H01L29/78, H01L29/786
CPC Code(s): H01L29/66553
Abstract: the present disclosure provides a semiconductor device and a method of forming the same. a semiconductor device according to the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a plurality of inner spacer features interleaving the plurality of channel members, a gate structure wrapping around each of the plurality of channel members, and a semiconductor liner sandwiched between the gate structure and each of the plurality of inner spacer features.
Inventor(s): Cheng-Chi Chuang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Lin-Yu Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Hao Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ting-Ya Lo of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Lin Teng of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Yen Huang of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/8234, H01L29/49, H01L29/78
CPC Code(s): H01L29/6656
Abstract: a semiconductor structure includes a substrate, a semiconductor layer, a gate stack, two first gate spacers over two opposing sidewalls of the gate stack and extending above the gate stack; a second gate spacer over a sidewall of one of the first gate spacers and having an upper portion over a lower portion; an etch stop layer adjacent to the lower portion and spaced away from the upper portion; and a seal layer over the gate stack, the two first gate spacers and the second gate spacer, resulting in a first void and a second void below the first seal layer. the first void is above the lower portion of the second gate spacer and laterally between the etch stop layer and the upper portion of the second gate spacer. the second void is above the gate stack and laterally between the two first gate spacers.
Inventor(s): Tsung-Lin LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Choh Fei YEAP of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Da-Wen LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chieh YEH of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/66, H01L21/02, H01L21/28, H01L21/764, H01L29/06, H01L29/423, H01L29/49, H01L29/786
CPC Code(s): H01L29/66742
Abstract: a method of fabricating a device includes providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interposed by a plurality of dummy layers. in some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source/drain region of the semiconductor device to form a trench in the source/drain region that exposes lateral surfaces of the plurality of semiconductor channel layers and the plurality of dummy layers. after forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch ends of the plurality of dummy layers to form first recesses along a sidewall of the trench. in some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the plurality of semiconductor channel layers and within the first recesses.
Inventor(s): Hsin-Fu LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hung LIU of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Tsung-Hao YEH of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/06, H01L29/66
CPC Code(s): H01L29/7816
Abstract: a semiconductor device includes a semiconductor layer, a drift region, a source area, a well region, a drain area, and a dielectric film. the drift region and the source area are formed in the semiconductor layer. the well region is formed in the semiconductor layer and between the drift region and the source area. the drain area is formed in the drift region. the dielectric film is formed in the drift region and is located between the source area and the drain area. the dielectric film includes a proximate end portion and a distal end portion which are proximate to and distal from the source area, respectively, and which are asymmetrical to each other.
Inventor(s): Yen-Chieh Huang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Po-Ting Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Hai-Ching Chen of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Sai-Hooi Yeong of Zhubei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Ming Lin of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te Lin of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/49, H01L29/786, H10B51/20
CPC Code(s): H01L29/78391
Abstract: a semiconductor device is described. the semiconductor device includes a blocking layer disposed on a channel of a substrate, a first seed layer disposed on the blocking layer, and a ferroelectric gate layer formed on the first seed layer. the first seed layer is arranged to increase a ratio of (o+t+c)/(o+t+c+m), in which o is the orthorhombic fraction of the ferroelectric gate layer, t is the tetragonal fraction of the ferroelectric gate layer, c is the cubic fraction of the ferroelectric gate layer, and m is the monoclinic fraction of the ferroelectric gate layer.
Inventor(s): Hung-Li CHIANG of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Chao LIN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chao-Ching CHENG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tzu-Chiang CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Tung-Ying LEE of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/8234, H01L29/06, H01L29/417, H01L29/66
CPC Code(s): H01L29/785
Abstract: a semiconductor device structure is provided. the semiconductor device structure includes a substrate. the semiconductor device structure includes a first nanostructure over the substrate. the semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. the semiconductor device structure includes a first source/drain structure and a second source/drain structure over the substrate. the gate stack is between the first source/drain structure and the second source/drain structure. the semiconductor device structure includes an inner spacer layer covering a sidewall of the first source/drain structure and partially between the gate stack and the first source/drain structure. the first nanostructure passes through the inner spacer layer. the semiconductor device structure includes a dielectric structure over the gate stack and extending into the inner spacer layer. the dielectric structure covers a top surface, an inner wall, and a lower surface of the inner spacer layer.
Inventor(s): Hsin-Yi LEE of Hsinchu 30072 (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-Lung HUNG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ji-Cheng CHEN of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Weng CHANG of Hsin-Chu 300 (TW) for taiwan semiconductor manufacturing company, ltd., Chi On CHUI of Hsinchu 30072 (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L29/417, H01L29/66
CPC Code(s): H01L29/785
Abstract: a semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. the semiconductor device includes a fin structure disposed on a substrate, a nanostructured channel region disposed on the fin structure, and a gate-all-around (gaa) structure surrounding the nanostructured channel region. the gaa structure includes a high-k (hk) gate dielectric layer with a metal doped region having dopants of a first metallic material, a p-type work function metal (pwfm) layer disposed on the hk gate dielectric layer, a bimetallic nitride layer interposed between the hk gate dielectric layer and the pwfm layer, an n-type work function metal (nwfm) layer disposed on the pwfm layer, and a gate metal fill layer disposed on the nwfm layer. the pwfm layer includes a second metallic material and the bimetallic nitride layer includes the first and second metallic materials.
Inventor(s): Yu-Kuan LIN of Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Ta YANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Wei WANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/308, H01L21/8238, H01L27/092, H01L29/06, H01L29/423, H01L29/66
CPC Code(s): H01L29/785
Abstract: methods for manufacturing a semiconductor device structure are provided. the method includes forming a first masking layer covering a first region and a second region and forming a second masking layer over the first masking layer, and the second masking layer includes a first pattern over the second region. the method further includes forming a third masking layer over the second masking layer, and the third masking layer includes a second pattern over the first region and transferring the second pattern of the third masking layer to the second masking layer to form a third pattern from the second masking layer. the method further includes transferring the first pattern and the third pattern of the second masking layer to the first masking layer to form a fourth pattern and a fifth pattern from the first masking layer over the first region and the second region, respectively.
Inventor(s): Chi-Yi Chuang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Hou-Yu Chen of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Lun Cheng of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/78, H01L21/02, H01L21/8234, H01L29/66
CPC Code(s): H01L29/7851
Abstract: a semiconductor device according to the present disclosure includes a first transistor and a second transistor disposed over the first transistor. the first transistor includes a plurality of channel members vertically stacked over one another, and a first source/drain feature adjoining the plurality of channel members. the second transistor includes a fin structure, and a second source/drain feature adjoining the fin structure. the semiconductor device further includes a conductive feature electrically connecting the first source/drain feature and the second source/drain feature.
Inventor(s): Shih-Hao Lin of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chong-De Lien of Taoyuan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Chuan Yang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Yu Hsu of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Shuan Li of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Hsin-Wen Su of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/786, H01L21/02, H01L21/8238, H01L27/092, H01L29/06, H01L29/161, H01L29/24, H01L29/423, H01L29/66, H10B10/00
CPC Code(s): H01L29/78618
Abstract: a method of fabricating a device includes providing a fin extending from a substrate in a device type region, where the fin includes a plurality of semiconductor channel layers. in some embodiments, the method further includes forming a gate structure over the fin. thereafter, in some examples, the method includes removing a portion of the plurality of semiconductor channel layers within a source/drain region adjacent to the gate structure to form a trench in the source/drain region. in some cases, the method further includes after forming the trench, depositing an adhesion layer within the source/drain region along a sidewall surface of the trench. in various embodiments, and after depositing the adhesion layer, the method further includes epitaxially growing a continuous first source/drain layer over the adhesion layer along the sidewall surface of the trench.
Inventor(s): Yu-Chu LIN of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Wen-Chih CHIANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Chung JEN of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Ming-Hong SU of Tainan (TW) for taiwan semiconductor manufacturing company, ltd., Mei-Chen SU of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Wei LEE of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Kuan-Wei SU of Kaohsiung (TW) for taiwan semiconductor manufacturing company, ltd., Chia-Ming PAN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H01L29/788, G11C16/04, G11C16/14, G11C16/26, H01L21/28, H01L29/423, H01L29/66, H10B41/10, H10B41/35, H10B41/70
CPC Code(s): H01L29/788
Abstract: some implementations described herein provide a semiconductor structure. the semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. the semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. the semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.
Inventor(s): Tsung-Hsien Tsai of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Jason Hsu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Ruey-Bin Sheen of Taichung City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H03L7/099, H03L7/187
CPC Code(s): H03L7/0992
Abstract: a tuning array selection circuit, together with a decoder and a voltage controlled oscillator (vco), can be employed to overcome some disadvantages of previous methods of phase locked loops. for example, a vco can include a coarse tuning array and a fine tuning array. a coarse tuning array can be used to tune a vco to generate a signal within a wide frequency range. a fine tuning array can be used to tune a vco to generate a signal within a narrow frequency range. in one embodiment, the narrow frequency range is within the wide frequency range. the tuning array selection circuit can coordinate selection of appropriate fine tuning devices and narrow tuning devices to reduce transition jitter and the risk of fail locking of phase locked loops.
Inventor(s): Shih-Lien Linus Lu of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kun-hsi Li of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Shih-Liang Wang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Jonathan Tsung-Yung Chang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Yu-Der Chih of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Cheng-En Lee of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H04L9/08, G06F7/58, H04L9/32
CPC Code(s): H04L9/0869
Abstract: systems and methods of generating a security key for an integrated circuit device include generating a plurality of key bits with a physically unclonable function (puf) device. the puf can include a random number generator that can create random bits. the random bits may be stored in a nonvolatile memory. the number of random bits stored in the nonvolatile memory allows for a plurality of challenge and response interactions to obtain a plurality of security keys from the puf.
Inventor(s): Hidehiro Fujiwara of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En Huang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yen-Huei Chen of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Yih Wang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C5/06, H01L27/092, H01L29/66, H01L29/78
CPC Code(s): H10B10/12
Abstract: a static random access memory (sram) cell includes a four-contact polysilicon pitch (4cpp) fin field effect transistor (finfet) architecture including a first bit-cell and a second bit cell. the sram cell includes a first bit line and a first complementary bit line, wherein the first bit line and the first complementary bit line are shared by the first and second bit-cells of the sram cell. the sram cell includes a first word line connected to the first bit cell, and a second word line connected to the second bit cell.
Inventor(s): Kuo-Hsiu Hsu of Taoyuan County (TW) for taiwan semiconductor manufacturing company, ltd., Feng-Ming Chang of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Kian-Long Lim of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd., Ping-Wei Wang of Hsin-Chu (TW) for taiwan semiconductor manufacturing company, ltd., Lien Jung Hung of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Ruey-Wen Chang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C7/12, G11C8/08, G11C11/412, G11C11/417
CPC Code(s): H10B10/12
Abstract: a semiconductor structure includes an sram cell that includes first and second pull-up (pu) transistors, first and second pull-down (pd) transistors, and first and second pass-gate (pg) transistors. a source, a drain, and a channel of the first pu transistor and a source, a drain, and a channel of the second pu transistor are collinear. a source, a drain, and a channel of the first pd transistor, a source, a drain, and a channel of the second pd transistor, a source, a drain, and a channel of the first pg transistor, and a source, a drain, and a channel of the second pg transistor are collinear.
Inventor(s): Gulbagh SINGH of Uttar Pradesh (IN) for taiwan semiconductor manufacturing company, ltd., Shun-Chi TSAI of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chih-Ming LEE of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Chi-Yen LIN of Tainan City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Hung LO of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B10/00, G11C11/412, H01L21/8234, H01L27/02, H01L29/06, H01L29/423
CPC Code(s): H10B10/12
Abstract: an ic structure includes a first gate strip and a first active region under the first gate strip and forming a first transistor with the first gate strip. from a top view, the first active region has opposite short sides and opposite long sides connecting the short sides and longer than the short sides. first one of the long sides has a first stepped top-view profile. second one of the long sides has a second stepped top-view profile. the first stepped top-view profile has more step rises than the second stepped top-view profile.
Inventor(s): Meng-Sheng CHANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Chia-En HUANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Wan-Hsueh CHENG of New Taipei City (TW) for taiwan semiconductor manufacturing company, ltd., Yao-Jen YANG of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., Yih WANG of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/20, G06F30/392, G11C17/16, G11C17/18, H01L23/522, H01L23/528
CPC Code(s): H10B20/20
Abstract: a structure includes first and second active areas, first and second gates and a data line. the first gate is continuous and crosses over the first active area and the second active area. the first gate corresponds to gate terminals of first and second transistors, and first source/drain regions of the first and the second active areas correspond to first source/drain terminals of the first and second transistors. the second gate includes first and second gate portions electrically isolated from each other. the first and second gate portions correspond to gate terminals of third and fourth transistors, respectively. the first gate portion crosses over the first active area, and the second gate portion crosses over the second active area. the first data line is coupled to the first source/drain regions of the first active area and the second active area.
Inventor(s): Jhon Jhy Liaw of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B20/20, G11C17/16, H01L23/525
CPC Code(s): H10B20/20
Abstract: a semiconductor structure includes first and second transistors each having a source terminal, a drain terminal, and a gate terminal. the semiconductor structure further includes a program line; a first metal plate over the first and the second transistors; a first insulator over the first metal plate; a second metal plate over the first insulator; a second insulator over the second metal plate; and a third metal plate over the second insulator. the first metal plate, the first insulator, and the second metal plate form a first anti-fuse element. the second metal plate, the second insulator, and the third metal plate form a second anti-fuse element. the source terminal of the first transistor is electrically connected to the first metal plate. the source terminal of the second transistor is electrically connected to the third metal plate. the program line is electrically connected to the second metal plate.
Inventor(s): Yu-Wei Jiang of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Chih Lai of Hsinchu County (TW) for taiwan semiconductor manufacturing company, ltd., TsuChing Yang of Taipei (TW) for taiwan semiconductor manufacturing company, ltd., Hung-Chang Sun of Kaohsiung City (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chang Chiang of Hsinchu City (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10B51/20, H01L29/24, H10B51/10, H10B51/30
CPC Code(s): H10B51/20
Abstract: a method of forming a device includes the following steps. a multi-layer stack is formed, wherein the multi-layer stack includes a plurality of dielectric layers and a plurality of first sacrificial layers stacked alternately. a first trench is formed in the multi-layer stack. a memory material layer is formed on a sidewall of the first trench. a channel layer is conformally on the sidewall of the first trench and over the memory material layer. a plurality of conductive pillars are formed in the first trench.
Inventor(s): Chang-Lin YANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chung-Te LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Sheng-Yuan CHANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Han-Ting LIN of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chien-Hua HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N50/01, H10B61/00, H10N50/80
CPC Code(s): H10N50/01
Abstract: a method for fabricating magnetoresistive random-access memory cells (mram) on a substrate is provided. the substrate is formed with a magnetic tunneling junction (mtj) layer thereon. when the mtj layer is etched to form the mram cells, there may be metal components deposited on a surface of the mram cells and between the mram cells by chemical reaction. the metal components are then removed by chemical reaction.
Inventor(s): Yuan-Tai TSENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Chang-Chih HUANG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd., Kuo-Chyuan TZENG of Hsinchu (TW) for taiwan semiconductor manufacturing company, ltd.
IPC Code(s): H10N70/00
CPC Code(s): H10N70/841
Abstract: a phase change memory device includes a first electrode, a second electrode, a phase change region, a first spacer and a second spacer. the second electrode is disposed over the first electrode. the phase change region is disposed between the first and second electrodes. the first spacer laterally covers the phase change region. the second spacer laterally covers the first spacer, and has a thermal conductivity smaller than that of the first spacer.
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. patent applications on October 17th, 2024
- TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
- B05C11/10
- F16K7/12
- F16K23/00
- F16K31/122
- F16K37/00
- H01L21/67
- B05C5/02
- B05C11/08
- G03F7/16
- G03F7/30
- CPC B05C11/1002
- Taiwan semiconductor manufacturing company, ltd.
- B24B37/04
- C09G1/02
- C09K3/14
- CPC B24B37/044
- B81B3/00
- B81C1/00
- H04R19/00
- H10N30/30
- CPC B81B3/001
- G01M3/02
- CPC G01M3/02
- G01N21/3504
- H01L21/66
- CPC G01N21/3504
- G01R1/04
- H01R12/70
- CPC G01R1/0433
- G01R27/16
- G01R31/30
- G01R31/319
- CPC G01R27/16
- G02B6/125
- G02B6/134
- CPC G02B6/125
- G02B6/136
- G02B6/12
- G02B6/122
- CPC G02B6/136
- G02F1/01
- H10N10/01
- H10N10/17
- H10N10/80
- H10N10/852
- H10N10/855
- CPC G02F1/0147
- G03F1/64
- CPC G03F1/64
- H01L21/033
- G03F7/38
- G03F7/004
- H01L21/027
- H01L21/311
- H01L21/3213
- CPC G03F7/38
- G03F7/00
- H05G2/00
- CPC G03F7/70858
- G05F3/20
- G05F3/26
- CPC G05F3/20
- G06F9/451
- G06F3/04847
- G06F8/38
- G06F40/109
- CPC G06F9/451
- G06F30/33
- G06F30/327
- CPC G06F30/33
- G06F30/392
- H01L27/088
- H01L29/78
- CPC G06F30/392
- G06F30/398
- CPC G06F30/398
- G11C11/16
- H10B61/00
- H10N50/10
- CPC G11C11/1675
- G11C11/4091
- G06F7/523
- G11C11/4094
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- CPC G11C11/4091
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- C23C14/18
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- C23C14/54
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- CPC H01J37/345
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- H01L29/417
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- CPC H01L21/20
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- CPC H01L21/26586
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- C23C16/452
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- CPC H01L21/311
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- H01L21/8234
- H01L27/092
- CPC H01L21/32139
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- CPC H01L21/67115
- G06F30/367
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- CPC H01L21/67248
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- CPC H01L21/67742
- H01L21/762
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- CPC H01L21/76254
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- H01L29/423
- H01L29/786
- CPC H01L21/7682
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- CPC H01L21/76897
- CPC H01L21/823456
- H01L21/8238
- CPC H01L21/823462
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- CPC H01L21/823481
- CPC H01L21/823828
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- CPC H01L21/823842
- CPC H01L22/12
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- CPC H01L23/3185
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- CPC H01L23/3675
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- CPC H01L23/3677
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- CPC H01L23/49838
- CPC H01L23/5227
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- H01L23/538
- CPC H01L23/5389
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- H01L27/02
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- CPC H01L25/0652
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- H01L27/12
- CPC H01L25/0657
- H01L23/528
- H01L27/07
- H01L29/10
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- CPC H01L27/0886
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- CPC H01L27/092
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- CPC H01L27/124
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- H01L23/552
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- H01G4/30
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- H01L27/08
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- CPC H01L28/91
- CPC H01L29/0665
- CPC H01L29/0673
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- CPC H01L29/0843
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- H01L21/3115
- CPC H01L29/401
- CPC H01L29/41733
- H01L29/165
- CPC H01L29/41791
- CPC H01L29/42376
- CPC H01L29/42392
- CPC H01L29/515
- H01L29/94
- CPC H01L29/66181
- CPC H01L29/66545
- CPC H01L29/66553
- CPC H01L29/6656
- H01L21/764
- CPC H01L29/66742
- CPC H01L29/7816
- H10B51/20
- CPC H01L29/78391
- CPC H01L29/785
- H01L21/308
- CPC H01L29/7851
- H01L29/161
- H01L29/24
- H10B10/00
- CPC H01L29/78618
- H01L29/788
- G11C16/04
- G11C16/14
- G11C16/26
- H10B41/10
- H10B41/35
- H10B41/70
- CPC H01L29/788
- H03L7/099
- H03L7/187
- CPC H03L7/0992
- H04L9/08
- G06F7/58
- H04L9/32
- CPC H04L9/0869
- G11C5/06
- CPC H10B10/12
- G11C7/12
- G11C8/08
- G11C11/412
- G11C11/417
- H10B20/20
- G11C17/16
- G11C17/18
- CPC H10B20/20
- H01L23/525
- H10B51/10
- H10B51/30
- CPC H10B51/20
- H10N50/01
- H10N50/80
- CPC H10N50/01
- H10N70/00
- CPC H10N70/841
