Samsung electronics co., ltd. (20240347487). SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE simplified abstract
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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
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SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240347487 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE
The abstract of the patent application describes an upper redistribution wiring layer in a semiconductor package that includes a protective layer with an opening exposing the uppermost redistribution wiring and a bonding pad on this wiring through the opening. The bonding pad consists of multiple plating patterns.
- The protective layer is provided on at least one upper insulating layer.
- The opening in the protective layer exposes a portion of the uppermost redistribution wiring.
- The bonding pad is located on the uppermost redistribution wiring through the opening.
- The bonding pad includes a first plating pattern with a via pattern and a pad pattern.
- There is a second plating pattern on the first plating pattern.
- A third plating pattern is present on the second plating pattern.
Potential Applications: - Semiconductor packaging industry - Electronics manufacturing
Problems Solved: - Protection of redistribution wiring - Enhanced bonding pad design
Benefits: - Improved reliability of semiconductor packages - Better electrical connections
Commercial Applications: Title: Advanced Semiconductor Packaging Solutions This technology can be used in the production of high-performance electronic devices, improving their overall quality and reliability in various industries.
Questions about the technology: 1. How does the protective layer enhance the performance of the semiconductor package? 2. What are the advantages of using multiple plating patterns in the bonding pad design?
Original Abstract Submitted
an upper redistribution wiring layer of a semiconductor package includes a protective layer provided on at least one upper insulating layer and having an opening that exposes at least a portion of an uppermost redistribution wiring among second redistribution wirings, and a bonding pad provided on the uppermost redistribution wiring through the opening. the bonding pad includes a first plating pattern formed on the uppermost redistribution wiring, the first plating pattern including a via pattern provided in the opening and a pad pattern formed on the via pattern to be exposed from the opening, a second plating pattern on the second plating pattern, and a third plating pattern on the second plating pattern.
