Samsung electronics co., ltd. (20240347435). SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD simplified abstract

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SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD

Organization Name

samsung electronics co., ltd.

Inventor(s)

Hyeonjeong Hwang of Suwon-si (KR)

Kyounglim Suk of Suwon-si (KR)

Seokhyun Lee of Suwon-si (KR)

SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240347435 titled 'SEMICONDUCTOR PACKAGE INCLUDING UNDER BUMP METALLIZATION PAD

The semiconductor package described in the patent application includes a semiconductor chip, a lower redistribution layer with insulating layers, redistribution patterns, and conductive vias, a lower passivation layer with a recess, an under bump metallization (UBM) pad in the recess, a UBM protective layer covering the UBM pad, and an outer connecting terminal.

  • The lower redistribution layer is made up of insulating layers, redistribution patterns, and conductive vias.
  • The lower passivation layer is located under the lower redistribution layer and has a recess at its bottom surface.
  • The UBM pad is placed in the recess and is connected to the lower conductive vias.
  • The UBM protective layer covers the UBM pad and is connected to the lower conductive vias.
  • The outer connecting terminal is connected to the bottom surface of the UBM pad.

Potential Applications: - This technology can be used in the manufacturing of advanced semiconductor packages for various electronic devices. - It can improve the performance and reliability of semiconductor chips in applications such as smartphones, computers, and automotive electronics.

Problems Solved: - The technology addresses the need for efficient and reliable connections between semiconductor chips and external components. - It provides enhanced protection and insulation for the semiconductor chip and its components.

Benefits: - Improved performance and reliability of semiconductor packages. - Enhanced connectivity and protection for semiconductor chips. - Increased efficiency in electronic devices.

Commercial Applications: Title: Advanced Semiconductor Packaging Technology for Enhanced Connectivity This technology can be utilized in the production of high-performance electronic devices, leading to improved functionality and durability. The market implications include increased demand for advanced semiconductor packages in various industries such as consumer electronics, telecommunications, and automotive.

Questions about Semiconductor Packaging Technology: 1. How does the lower redistribution layer contribute to the overall performance of the semiconductor package? The lower redistribution layer plays a crucial role in facilitating efficient signal routing and power distribution within the semiconductor package, enhancing its overall functionality and reliability.

2. What are the key advantages of using an under bump metallization (UBM) pad in semiconductor packaging? The UBM pad provides a reliable and robust connection between the semiconductor chip and external components, improving the electrical performance and longevity of the semiconductor package.


Original Abstract Submitted

a semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (ubm) pad disposed in the first recess, a ubm protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the ubm pad, and an outer connecting terminal connected to a bottom surface of the ubm pad. the bottom surface of the ubm pad is positioned at a first depth from the bottom surface of the lower passivation layer.