Samsung electronics co., ltd. (20240347085). RECEIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME simplified abstract
Contents
RECEIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME
Organization Name
Inventor(s)
Changhyun Bae of Suwon-si (KR)
RECEIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240347085 titled 'RECEIVERS AND SEMICONDUCTOR MEMORY DEVICES INCLUDING THE SAME
The abstract of the patent application describes a receiver that includes a buffer, decision feedback equalizer, deserializer, and reset control circuit.
- The buffer generates an internal data signal by comparing received data with a reference voltage.
- The decision feedback equalizer generates a sampled signal based on the internal data signal and a feedback signal, providing either the sampled signal or a logic level as the feedback signal based on a reset control signal.
- The deserializer generates output data by deserializing the sampled signal.
- The reset control circuit generates the reset control signal based on operating information related to a write operation of the data signal and provides it to the decision feedback equalizer.
Potential Applications: - This technology can be used in communication systems to improve the reception and processing of data signals. - It can be applied in high-speed data transmission systems to enhance signal integrity and reduce errors.
Problems Solved: - Enhances the accuracy and reliability of data reception and processing. - Improves the performance of communication systems by reducing signal distortion and noise.
Benefits: - Increased data transmission efficiency and reliability. - Enhanced signal processing capabilities for better overall system performance.
Commercial Applications: Title: Advanced Data Receiver Technology for Communication Systems This technology can be utilized in telecommunications, networking equipment, data centers, and other industries that rely on high-speed data transmission.
Questions about the technology: 1. How does the decision feedback equalizer improve signal processing in the receiver? 2. What are the key advantages of using a reset control circuit in this receiver technology?
Original Abstract Submitted
a receiver includes a buffer configured to generate an internal data signal by comparing a received data signal with a reference voltage, a decision feedback equalizer configured to generate a sampled signal based on a present value of the internal data signal and on a feedback signal, and configured to provide one of the sampled signal or a first logic level as the feedback signal based on a reset control signal, the sampled signal corresponding to a previous value of the internal data signal, a deserializer configured to generate an output data by deserializing the sampled signal, and a reset control circuit configured to generate the reset control signal based on operating information associated with a write operation of the data signal and configured to provide the reset control signal to the decision feedback equalizer.
