Samsung electronics co., ltd. (20240321755). SEMICONDUCTOR PACKAGE INCLUDING GLASS CORE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME simplified abstract

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SEMICONDUCTOR PACKAGE INCLUDING GLASS CORE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Organization Name

samsung electronics co., ltd.

Inventor(s)

Myungsam Kang of Suwon-si (KR)

SEMICONDUCTOR PACKAGE INCLUDING GLASS CORE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240321755 titled 'SEMICONDUCTOR PACKAGE INCLUDING GLASS CORE SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

The semiconductor package described in the patent application aims to reduce the size of a silicon interposer and minimize warpage of the package substrate, all while maintaining chip-to-chip connection functionality.

  • The package substrate consists of a glass core substrate, a silicon bridge interposer, and a multi-layer wiring layer beneath the glass core substrate and the silicon bridge interposer.
  • At least two semiconductor devices are stacked on the package substrate, with a cavity formed in the central portion of the glass core substrate, where the silicon bridge interposer is embedded.
  • The innovation lies in embedding the silicon bridge interposer in the cavity of the glass core substrate, allowing for a more compact design and reduced warpage.
  • This design enables efficient chip-to-chip connections while optimizing space utilization and minimizing substrate warpage.

Potential Applications: - This technology can be applied in various semiconductor packaging processes where space optimization and substrate warpage reduction are crucial.

Problems Solved: - Minimizes the size of a silicon interposer - Reduces warpage of the package substrate - Maintains chip-to-chip connection functionality

Benefits: - Compact design - Improved substrate flatness - Enhanced chip-to-chip connection reliability

Commercial Applications: - This technology can be utilized in the production of advanced semiconductor packages for various electronic devices, such as smartphones, tablets, and computers.

Questions about the technology: 1. How does embedding the silicon bridge interposer in the glass core substrate cavity contribute to reducing package size? 2. What are the key advantages of minimizing substrate warpage in semiconductor packaging processes?


Original Abstract Submitted

provided is a semiconductor package capable of minimizing the size of a silicon (si) interposer and minimizing warpage of a package substrate while maintaining a chip-to-chip connection function. the semiconductor package includes a package substrate including a glass core substrate, a silicon (si) bridge interposer, and a multi-layer wiring layer disposed under the glass core substrate and the si bridge interposer, and at least two semiconductor devices stacked on the package substrate, wherein a cavity is formed in a central portion of the glass core substrate, and the si bridge interposer is embedded in the cavity.

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