Samsung electronics co., ltd. (20240319874). MEMORY DEVICE COMPRESSING SOFT DECISION DATA AND OPERATING METHOD THEREOF simplified abstract
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MEMORY DEVICE COMPRESSING SOFT DECISION DATA AND OPERATING METHOD THEREOF
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MEMORY DEVICE COMPRESSING SOFT DECISION DATA AND OPERATING METHOD THEREOF - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240319874 titled 'MEMORY DEVICE COMPRESSING SOFT DECISION DATA AND OPERATING METHOD THEREOF
The memory device described in the abstract includes two memory cell arrays, two page buffers for reading data from the arrays, and a compression circuit for compressing soft decision data.
- The first memory cell array and second memory cell array store data.
- The first page buffer and second page buffer read data from their respective memory cell arrays.
- The first compression circuit compresses first soft decision data by encoding the location of a bit with a specific value.
- The compression circuit works while second hard decision data is being output from the second memory cell array.
- The compression process involves using soft read voltages for the first memory cell array and a hard read voltage for the second memory cell array.
Potential Applications: - Data storage systems - Communication systems - Signal processing applications
Problems Solved: - Efficient data compression - Enhanced memory device performance - Improved data retrieval processes
Benefits: - Increased data storage capacity - Faster data processing speeds - Enhanced overall system performance
Commercial Applications: Title: Advanced Data Compression Technology for Memory Devices This technology can be utilized in various industries such as telecommunications, data centers, and consumer electronics for improved data storage and processing capabilities.
Prior Art: Researchers can explore prior patents related to memory devices, data compression techniques, and signal processing technologies to understand the existing knowledge in this field.
Frequently Updated Research: Stay updated on advancements in memory device technology, data compression algorithms, and signal processing methods to leverage the latest innovations in the field.
Questions about Memory Device Compression Technology: 1. How does the compression circuit in the memory device improve data storage efficiency? 2. What are the potential implications of using soft read voltages and hard read voltages in memory cell arrays for data compression?
Original Abstract Submitted
a memory device includes a first memory cell array and a second memory cell array, a first page buffer and a second page buffer configured to read data from the first memory cell array and the second memory cell array, respectively; and a first compression circuit configured to compress first soft decision data into first compressed data by encoding a location of a bit having a first value among bits of the first soft decision data, the first soft decision data being obtained from the first memory cell array by using a plurality of soft read voltages, wherein the first compression circuit is further configured to compress the first soft decision data into the first compressed data while second hard decision data is being output, the second hard decision data being read from the second memory cell array by using a hard read voltage.
