Samsung electronics co., ltd. (20240312920). SEMICONDUCTOR PACKAGE simplified abstract
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240312920 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the abstract consists of a first redistribution structure with at least one redistribution layer and one insulating layer, a first semiconductor chip, a second semiconductor chip, and bumps between the redistribution structure and the chips. The first redistribution layer includes a detour redistribution line that overlaps a space between the chips, avoiding a stress concentration region.
- The semiconductor package includes a unique detour redistribution line that circuitously extends across the space between the first and second semiconductor chips.
- The detour redistribution line prevents overlap with a stress concentration region, enhancing the reliability of the package.
- Bumps are strategically placed between the redistribution structure and the semiconductor chips to ensure proper connections.
- The design of the semiconductor package aims to improve the overall performance and durability of the chips.
- By optimizing the layout of the redistribution structure and incorporating detour lines, the package minimizes stress concentration and potential failure points.
Potential Applications: This technology can be applied in various semiconductor devices, such as microprocessors, memory chips, and sensors.
Problems Solved: The semiconductor package addresses issues related to stress concentration and potential failure points in traditional packaging designs.
Benefits: Enhanced reliability and performance of semiconductor chips, improved durability, and reduced risk of failure.
Commercial Applications: This technology can be utilized in the manufacturing of consumer electronics, automotive electronics, and industrial equipment.
Questions about the technology: 1. How does the detour redistribution line contribute to the reliability of the semiconductor package? 2. What are the potential challenges in implementing this innovative packaging design in mass production?
Original Abstract Submitted
a semiconductor package includes: a first redistribution structure having a structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip disposed on the first redistribution structure; a second semiconductor chip disposed on the first redistribution structure; and bumps disposed between the first redistribution structure and the first semiconductor chip and between the first redistribution structure and the second semiconductor chip, wherein the at least one first redistribution layer includes a detour redistribution line disposed so that a portion of the detour redistribution line overlaps a space between the first and second semiconductor chips, and the detour redistribution line circuitously extends across the space between the first and second semiconductor chips so as not to overlap a stress concentration region partially overlapping a portion of the space between the first and second semiconductor chips, or extends into the stress concentration region.
