Samsung electronics co., ltd. (20240284673). MEMORY DEVICE simplified abstract
Contents
MEMORY DEVICE
Organization Name
Inventor(s)
Takuya Futatsuyama of Suwon-si (KR)
Daeseok Byeon of Suwon-si (KR)
MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240284673 titled 'MEMORY DEVICE
The memory device described in the patent application consists of a first cell region with first memory strings, a second cell region with second memory strings, and a peripheral circuit region that controls both sets of memory strings.
- The first cell region includes a low-level bit line connected to the first memory strings.
- A low-level bonding pad is situated between the peripheral circuit region and the first cell region.
- A low-level connection via is connected to the low-level bonding pad.
- A high-level bonding pad is located between the first and second cell regions.
- The second cell region features a high-level bit line connected to the second memory strings.
- A high-level connection via is connected to the high-level bonding pad, offset laterally from the low-level connection via.
Potential Applications: - Data storage devices - Embedded systems - Consumer electronics
Problems Solved: - Efficient memory storage and retrieval - Improved data processing speed - Enhanced overall device performance
Benefits: - Increased memory capacity - Faster data access - Enhanced device functionality
Commercial Applications: Title: "Advanced Memory Devices for High-Performance Electronics" This technology can be utilized in smartphones, tablets, laptops, and other electronic devices to improve memory storage and processing capabilities, leading to faster and more efficient performance in various applications.
Questions about the technology: 1. How does the lateral offset of the high-level connection via from the low-level connection via impact memory device performance? 2. What are the specific advantages of having separate cell regions with different memory strings in the memory device architecture?
Original Abstract Submitted
a memory device is disclosed. the memory device includes a first cell region including first memory strings, a second cell region attached to the first cell region and including second memory strings, and a peripheral circuit region attached to the first cell region and including a peripheral circuit configured to control the first and second memory strings, the first cell region including a low-level bit line electrically connected to the first memory strings, a low-level bonding pad provided between the peripheral circuit region and the first cell region, a low-level connection via connected to the low-level bonding pad, a high-level bonding pad provided between the first and second cell regions, the second cell region including a high-level bit line electrically connected to the second memory strings, and a high-level connection via connected to the high-level bonding pad and being laterally offset from the low-level connection via.
