Samsung electronics co., ltd. (20240258224). SEMICONDUCTOR PACKAGE simplified abstract
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Seungryong Oh of Suwon-si (KR)
Seunghoon Yeon of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240258224 titled 'SEMICONDUCTOR PACKAGE
The semiconductor package described in the abstract includes a package-bottom redistribution structure, an upper semiconductor chip, an upper back end of line (BEOL) layer, a lower semiconductor chip, a lower BEOL layer, a passivation layer, and a through silicon via (TSV) structure.
- The package-bottom redistribution structure contains a conductive line.
- The upper semiconductor chip is located at the top of the package.
- The upper BEOL layer, situated beneath the upper semiconductor chip, includes a conductive line.
- The lower semiconductor chip is positioned below the upper semiconductor chip, with a smaller horizontal width.
- The upper semiconductor chip overlaps with at least a portion of the lower semiconductor chip.
- The lower BEOL layer, located beneath the lower semiconductor chip, contains a conductive line.
- A passivation layer covers the upper surface of the lower semiconductor chip.
- A TSV structure penetrates the passivation layer and the lower semiconductor chip.
Potential Applications: - Advanced semiconductor packaging technology for high-performance electronic devices. - Improved integration of multiple semiconductor chips in a compact package design.
Problems Solved: - Enhancing the performance and functionality of semiconductor packages. - Facilitating efficient communication between stacked semiconductor chips.
Benefits: - Increased functionality and performance of electronic devices. - Enhanced reliability and durability of semiconductor packages.
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for High-Performance Electronics This technology can be utilized in various industries such as telecommunications, computing, and automotive for the development of high-performance electronic devices with compact and efficient semiconductor packaging.
Questions about the technology: 1. How does the overlap of the upper and lower semiconductor chips impact the overall performance of the package? 2. What are the advantages of using a TSV structure in this semiconductor packaging design?
Original Abstract Submitted
a semiconductor package includes a package-bottom redistribution structure at a lower side of a package and including a conductive line, an upper semiconductor chip at an upper side of the package, an upper back end of line (beol) layer, at a lower side of the upper semiconductor chip, and including a conductive line, a lower semiconductor chip below the upper semiconductor chip, where a horizontal width of the lower semiconductor chip is less than a horizontal width of the upper semiconductor chip, and where the upper semiconductor chip overlaps at least a portion of the lower semiconductor chip, a lower beol layer at a lower side of the lower semiconductor chip and including a conductive line, a passivation layer on an upper surface of the lower semiconductor chip, and a through silicon via (tsv) structure penetrating the passivation layer and the lower semiconductor chip.
