SK hynix Inc. patent applications on September 19th, 2024
Patent Applications by SK hynix Inc. on September 19th, 2024
SK hynix Inc.: 26 patent applications
SK hynix Inc. has applied for patents in the areas of H10B41/27 (5), G11C16/04 (5), H10B43/27 (5), G11C16/10 (4), H10B43/10 (3) H10B43/27 (4), G03F1/30 (1), H01L27/14634 (1), H10N50/10 (1), H04N25/46 (1)
With keywords such as: memory, layer, cell, circuit, device, signal, configured, voltage, electrode, and forming in patent application abstracts.
Patent Applications by SK hynix Inc.
Inventor(s): Tae Joong HA of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G03F1/30
CPC Code(s): G03F1/30
Abstract: there is provided a phase shift mask for extreme-ultraviolet lithography and a method of manufacturing the phase shift mask. the phase shift mask includes a substrate, a reflective layer, device patterns, a frame pattern, or phase shift patterns. the frame pattern is a pattern that includes alignment holes exposing portions of the reflective layer. the phase shift patterns overlap with the device patterns.
Inventor(s): Ji Hun CHOI of Icheon (KR) for sk hynix inc., Jeong Hyun KIM of Icheon (KR) for sk hynix inc., Sung Ju YOO of Icheon (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a memory controller includes a buffer, a prefetch controller, and a boot controller. the buffer stores workload information including a history of an expected i/o request expected to be received from a host during booting operation. the prefetch controller is configured to, before a target i/o request is received from the host after start of booting, read expected data corresponding to the expected i/o request from memory devices based on workload information, and store the expected data in the buffer. the boot controller updates the workload information based on the target i/o request depending on whether target data corresponding to the target i/o request is included in the expected data, and stores updated workload information in an area in which data is readable with a minimum number of accesses from a plurality of the memory devices.
20240311056. MEMORY CONTROLLER AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Hyun Sub KIM of Seongnam (KR) for sk hynix inc., Ie Ryung PARK of Suwon (KR) for sk hynix inc., Dong Sop LEE of Yongin (KR) for sk hynix inc., Sung Yeob CHO of Yongin (KR) for sk hynix inc.
IPC Code(s): G06F3/06, G11C11/56, G11C16/04
CPC Code(s): G06F3/0659
Abstract: a memory controller may include: a request checker identifying memory devices corresponding to requests received from a host among the plurality of memory devices and generating device information on the identified memory devices to perform operations corresponding to the requests; a dummy manager outputting a request for controlling a dummy pulse to be applied to channels of selected memory devices according to the device information among the plurality of channels; and a dummy pulse generator sequentially applying the dummy pulse to the channels coupled to the selected memory devices, based on the request for controlling the dummy pulse. a memory controller may include an idle time monitor outputting an idle time interval of the memory device and a clock signal generator generating a clock signal based on the idle time interval and outputting the clock signal to the memory device through the channel to perform a current operation.
Inventor(s): Mino KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Sungwoo LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/12, G11C7/10, G11C7/22
CPC Code(s): G11C7/12
Abstract: a semiconductor apparatus includes a power gating control circuit and a power gating circuit. the power gating control circuit generates a power gating signal based on an idle signal, a clock synchronization signal, and a delayed idle signal. the power gating circuit applies at least a first operating voltage to an internal circuit based on the power gating signal.
Inventor(s): Ji Hyo KANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C7/22, G11C7/10
CPC Code(s): G11C7/222
Abstract: a clock distribution network includes at least two buffers that receive the same clock signal and generate different clock signals. in a first operation mode, the at least two buffers are all activated. in a second operation mode, one of the at least two buffers is activated. in the second operation mode, the other one of the at least two buffers is partially activated without being deactivated.
Inventor(s): Sang Hyun KU of Gyeonggi-do (KR) for sk hynix inc., Do Hong KIM of Gyeonggi-do (KR) for sk hynix inc., Duck Hwa HONG of Gyeonggi-do (KR) for sk hynix inc., Min Ho SEOK of Gyeonggi-do (KR) for sk hynix inc., So Yoon KIM of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C8/08
CPC Code(s): G11C8/08
Abstract: a memory device includes a plurality of word lines; and a row control circuit configured to: drive, in response to a precharge command, a selected word line of the word lines such that a voltage level of the selected word line decreases from a first voltage level to a second voltage level during a first section, stays at the second voltage level during a second section and decreases from the second voltage level to a third voltage level during a third section, and keep the second section at a preset time amount, or change the second section to a time amount defined by an input of an active command according to a mode control signal.
Inventor(s): Choung Ki SONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C11/4072, G11C11/4076, G11C11/408, G11C11/4093, H01L23/00, H01L25/18, H10B80/00
CPC Code(s): G11C11/4072
Abstract: a buffer chip may include: a chip select signal reception circuit configured to receive system chip select signals transmitted from a memory controller; a chip select signal mapping circuit configured to generate memory chip select signals by mapping the system chip select signals by using failed memory chip information; and a chip select signal transmission circuit configured to transmit the memory chip select signals to a plurality of memory chips.
Inventor(s): Sung Hyun HWANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jae Yeop JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Se Chun PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/04
CPC Code(s): G11C16/10
Abstract: a memory device applies voltage to drain select lines, which are determined individually. a program operation control unit applies a precharge voltage to a drain select line coupled to a cell string selected from the first cell string and the second cell string before a program voltage is applied to the word line, during a time determined depending on a resistance value of the drain select line coupled to the selected cell string.
Inventor(s): Hyung Jin CHOI of Gyeonggi-do (KR) for sk hynix inc., In Gon YANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/08, G11C16/24
CPC Code(s): G11C16/102
Abstract: provided herein may be a semiconductor memory device. the semiconductor memory device may include first and second cell strings. the first cell string is coupled to a first bit line and includes a first drain select transistor, a plurality of memory cells, and a first source select transistor. the second cell string is coupled to the first bit line and includes a second drain select transistor, a plurality of memory cells, and a second source select transistor. a plurality of data bits may be stored in a memory cell group formed by a first memory cell coupled to a first word line among memory cells included in the first cell string, and a second memory cell coupled to the first word line among memory cells included in the second cell string. the number of data bits stored in each of first and second memory cells may be a non-integer.
Inventor(s): Jun Young KWEON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/04
CPC Code(s): G11C16/3445
Abstract: provided herein may be a memory device for performing an erase verify operation on a cell string group basis, and method of operating the same. the memory device may include a plurality of memory blocks, each including a plurality of cell string groups, a peripheral circuit configured to perform an erase verify operation on a memory block selected from among the plurality of memory blocks, and an erase operation controller configured to control the peripheral circuit to perform the erase verify operation in units of cell string groups within the selected memory block. the erase operation controller controls the peripheral circuit to apply, during the erase verify operation, different erase verify voltages to the selected memory block whenever the erase verify operation is performed on each of the cell string groups.
Inventor(s): Sung Hyun HWANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Hyun Seob SHIN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jae Yeop JUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/08, G11C16/10
CPC Code(s): G11C16/3495
Abstract: a semiconductor device may include a plurality of transfer circuits configured to transfer a program pulse to at least one of a plurality of word lines based on a transfer control signal, a decoder configured to provide the program pulse to at least one of the plurality of transfer circuits based on a row address, and a control circuit configured to adjust a voltage level of the transfer control signal based on a program/erase count.
Inventor(s): Young Gwang YOON of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L21/28, H01L21/8234, H01L29/423
CPC Code(s): H01L21/28097
Abstract: a method for fabricating a mos transistor includes: forming a gate dielectric material layer over a substrate; forming a lower gate electrode material layer over the gate dielectric material layer; performing a first ion bombardment process of bombarding the lower gate electrode material layer with first ions; forming an intermediate gate electrode material layer including an amorphous silicon layer over the lower gate electrode material layer; forming an upper gate electrode material layer over the intermediate gate electrode material layer; performing a second ion bombardment process for bombarding the upper gate electrode material layer with second ions; and forming silicide layers in the lower gate electrode material layer and the upper gate electrode material layer to form a lower gate electrode layer and an upper gate electrode layer.
20240313023. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Jae Hyung JANG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): H01L27/146
CPC Code(s): H01L27/14634
Abstract: an image sensing device includes a first substrate and a second substrate. the first substrate includes a first infrared photoelectric conversion element structured to respond to infrared light to generate photocharges corresponding to an intensity of infrared light received by the first infrared photoelectric conversion element, and a color photoelectric conversion element structured to respond to visible light to generate photocharges corresponding to an intensity of visible light received by the color photoelectric conversion element. the second substrate stacked on the first substrate and configured to include a second infrared photoelectric conversion element structured to respond to infrared light to generate photocharges corresponding to an intensity of infrared light that passes through the first infrared photoelectric conversion element and is received by the second infrared photoelectric conversion element.
Inventor(s): Se Hun KANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/51, H10B53/30, H10B51/20
CPC Code(s): H01L28/56
Abstract: a semiconductor device includes a first electrode, a second electrode, and a multi-layer stack positioned between the first electrode and the second electrode, the multi-layer stack including at least one anti-ferroelectric layer and at least one high-k dielectric layer.
Inventor(s): Jae Hyun HAN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Won Tae KOO of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L29/423, H01L21/28, H10B41/27, H10B43/27
CPC Code(s): H01L29/42332
Abstract: a semiconductor memory device includes a channel layer, a gate electrode spaced apart from the channel layer, a blocking insulating layer between the gate electrode and the channel layer, a tunnel insulating layer between the channel layer and the blocking insulating layer, and nano-particles spaced apart from each other between the tunnel insulating layer and the blocking insulating layer.
Inventor(s): Seung Han OAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H03K5/24, H03F3/45, H03K19/0185
CPC Code(s): H03K5/2481
Abstract: a circuit for sensing and amplifying a signal of a signal line includes a sensing voltage generation circuit including a sensing circuit, the sensing voltage generation circuit configured to generate a sensing voltage by sensing and amplifying a line input signal based on a bias voltage, and a bias voltage generation circuit including a replication circuit, the replication circuit having a structure identical to a structure of the sensing circuit and generating a replication voltage and the bias voltage generation circuit configured to generate the bias voltage by comparing the replication voltage with a logic threshold level.
Inventor(s): Seung Ho LEE of Seoul (KR) for sk hynix inc.
IPC Code(s): H03K19/003, H03K19/00, H03K19/017, H03K19/17788
CPC Code(s): H03K19/00315
Abstract: a memory system may include a memory device and a memory controller. the memory device may be configured to store data. the memory controller may be configured to communicate with the memory device by an input/output driving circuit. the input/output driving circuit comprises a pull-down driver and a gate control logic. the pull-down driver may include a first transistor and a second transistor which are electrically coupled between a pad and a ground node. the gate control logic including a third transistor and a fourth transistor which are electrically coupled 10 between the pad and a first terminal receiving a first driving voltage, the gate control logic being configured to receive a pad voltage provided from the pad and generate a feedback voltage. the source voltage level of the second transistor is controlled by a control signal generated based on a clock signal and an enable signal.
Inventor(s): Fan ZHANG of San Jose CA (US) for sk hynix inc., Meysam ASADI of San Jose CA (US) for sk hynix inc., Haobo WANG of San Jose CA (US) for sk hynix inc.
IPC Code(s): H03M13/11, G06F11/10
CPC Code(s): H03M13/1105
Abstract: decoding method and memory system that classify check nodes in a matrix having irregular check node weights into different groups according to the check node weights, apply different scaling factors to respective constant node to variable node (c2v) messages in the different groups of the check nodes, and optionally add a compensation term to at least one of the c2v messages of the ms decoder.
20240314004. SYSTEM AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Jong Heon JEONG of Icheon (KR) for sk hynix inc.
IPC Code(s): H04L25/03
CPC Code(s): H04L25/03878
Abstract: a system includes a first device including a first transmitter and a first receiver, and a second device including a second transmitter and a second receiver and configured to communicate with the first device. the two devices perform a first equalization operation by performing a first phase in which the first receiver performs a signal tuning operation on the second transmitter, a second phase in which the second receiver performs a signal tuning operation on the first transmitter, and one or more other phases. the first, second, and other phases may constitute all the phases of the first equalization operation, and some of the other phases may precede the first and second phases. in response to detection of an error after the first equalization operation, the two devices may perform a second equalization operation by performing the first phase, the second phase, or both, but not performing the other phases.
Inventor(s): Cheol Jon JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N25/46
CPC Code(s): H04N25/46
Abstract: an image signal processor capable of performing image processing and a method for processing an image signal are disclosed. the image signal processor includes an image binning circuit configured to generate a second image by summing pixel values of color pixels in a first image including a pixel value of at least one phase detection pixel and the pixel values of the color pixels, a directionality strength determiner configured to calculate directionality strength information based on a target pixel disposed at a center of a target kernel within the target kernel of the second image, a pixel value comparator configured to compare the pixel value of the target pixel with pixel values of neighboring homogeneous pixels, a correction value generator configured to generate a correction value for correcting the target pixel, and a corrector configured to correct the target pixel.
20240315022. MEMORY DEVICE AND STORAGE DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Dong Hun KWAK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, G06F3/06, G11C11/56, G11C16/04, G11C16/10, H10B41/27, H10B41/41, H10B43/40
CPC Code(s): H10B43/27
Abstract: according to an embodiment of the present disclosure, a memory device may include a memory cell array including memory cells stacked in a direction perpendicular to a substrate, each of the memory cells including a first sub-memory cell and a second sub-memory cell having a size larger than a size of the first sub-memory cell, a sub-memory cell information storage configured to store sub-memory cell size information on the sizes of the first sub-memory cell and the second sub-memory cell, a peripheral circuit configured to perform a program operation on a selected sub-memory cell among the memory cells, and a control logic configured to control the peripheral circuit to store data in each of the first sub-memory cell and the second sub-memory cell based on the sub-memory cell size information.
Inventor(s): Hyun Ho LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/10, H10B41/27, H10B43/10, H10B63/00
CPC Code(s): H10B43/27
Abstract: a semiconductor device and a method of manufacturing same may include a stack including alternately stacked conductive layers and insulating layers, a separation insulating structure passing through the stack, and including a line pattern, first protrusion patterns protruded from the line pattern to one side, and second protrusion patterns protruded from the line pattern to another side, first channel structures passing through the stack at the one side of the separation insulating structure and surrounding the first protrusion patterns, respectively, and second channel structures passing through the stack at the another side of the separation insulating structure and surrounding the second protrusion patterns, respectively.
Inventor(s): Yoo Hyun NOH of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H01L23/528, H10B41/10, H10B41/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: a method for fabricating a semiconductor device includes forming a source structure over a lower structure with interconnections; forming a first contact plug that penetrates the source structure to be coupled to the interconnections, and a first sacrificial pad that penetrates the source structure and is spaced apart from the first contact plug; forming an upper structure that covers the first sacrificial pad, the first contact plug, and the source structure; forming a second contact plug that penetrates the upper structure and contacts the first contact plug, forming a second sacrificial pad that penetrates the upper structure to contact the first sacrificial pad and is spaced apart from the second contact plug; and replacing the first sacrificial pad and the second sacrificial pad with a dielectric supporter.
Inventor(s): Yoo Hyun NOH of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H01L23/522, H01L23/528, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/35
CPC Code(s): H10B43/27
Abstract: a method for fabricating a semiconductor device includes preparing a lower structure including an interconnection, forming a first contact plug coupled to the interconnection, and forming an alternating stack of dielectric layers and sacrificial layers over the first contact plug and the lower structure. the method further includes forming an opening that penetrates the alternating stack and exposes the first contact plug, forming a sacrificial plug including a void in the opening, forming a contact hole that exposes the first contact plug by etching a portion of the sacrificial plug, and forming a second contact plug in the contact hole.
Inventor(s): Yong Hun SUNG of Icheon (KR) for sk hynix inc.
IPC Code(s): H10N70/00, H10B63/00
CPC Code(s): H10N70/841
Abstract: a method for fabricating a semiconductor device includes forming a lower electrode layer containing carbon by applying ac power; forming a memory layer over the lower electrode layer; and forming an upper electrode layer containing carbon over the memory layer without applying ac power.
- SK hynix Inc.
- G03F1/30
- CPC G03F1/30
- Sk hynix inc.
- G06F3/06
- CPC G06F3/0655
- G11C11/56
- G11C16/04
- CPC G06F3/0659
- G11C7/12
- G11C7/10
- G11C7/22
- CPC G11C7/12
- CPC G11C7/222
- G11C8/08
- CPC G11C8/08
- G11C11/4072
- G11C11/4076
- G11C11/408
- G11C11/4093
- H01L23/00
- H01L25/18
- H10B80/00
- CPC G11C11/4072
- G11C16/10
- CPC G11C16/10
- G11C16/08
- G11C16/24
- CPC G11C16/102
- G11C16/34
- CPC G11C16/3445
- CPC G11C16/3495
- H01L21/28
- H01L21/8234
- H01L29/423
- CPC H01L21/28097
- H01L27/146
- CPC H01L27/14634
- H01L29/51
- H10B53/30
- H10B51/20
- CPC H01L28/56
- H10B41/27
- H10B43/27
- CPC H01L29/42332
- H03K5/24
- H03F3/45
- H03K19/0185
- CPC H03K5/2481
- H03K19/003
- H03K19/00
- H03K19/017
- H03K19/17788
- CPC H03K19/00315
- H03M13/11
- G06F11/10
- CPC H03M13/1105
- H04L25/03
- CPC H04L25/03878
- H04N25/46
- CPC H04N25/46
- H10B41/41
- H10B43/40
- CPC H10B43/27
- H10B41/10
- H10B43/10
- H10B63/00
- H01L23/528
- H01L23/522
- H10B41/35
- H10B43/35
- H10N70/00
- CPC H10N70/841
