SK hynix Inc. patent applications on August 8th, 2024
Patent Applications by SK hynix Inc. on August 8th, 2024
SK hynix Inc.: 21 patent applications
SK hynix Inc. has applied for patents in the areas of G11C16/24 (5), G11C16/10 (4), G11C16/04 (4), G06F3/06 (3), G11C16/08 (3) G11C16/3427 (2), G11C16/08 (2), G11C16/102 (1), H10B43/27 (1), H04N23/81 (1)
With keywords such as: memory, line, control, signal, including, device, circuit, cells, configured, and voltage in patent application abstracts.
Patent Applications by SK hynix Inc.
20240264038. PROBE CARD_simplified_abstract_(sk hynix inc.)
Inventor(s): Sung Wook CHO of Icheon-si (KR) for sk hynix inc., Yeon Su YEO of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G01M11/02, G01R1/073, G01R31/28
CPC Code(s): G01M11/0214
Abstract: probe cards that can replace lens units are disclosed. in some implementations, a probe card may include a lens unit through which light irradiated from a light source unit; a jig into which the lens unit is inserted inside, and a holder unit for closely supporting the lens unit.
20240264281. IMAGE SENSING DEVICE_simplified_abstract_(sk hynix inc.)
Inventor(s): Jae Hyung JANG of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G01S7/481, G01S17/894, H01L27/146, H04N25/77
CPC Code(s): G01S7/4816
Abstract: an image sensing device includes a pixel array including pixels, each pixel structured to respond to incident light to produce photocharges indicative of detected incident light. the pixel array includes: a first detection structure configured to include a first control node receiving a first demodulation control signal and a first detection node disposed to surround the first control node; a second detection structure configured to include a second control node receiving a second demodulation control signal and a second detection node disposed to surround the second control node; a first storage diode electrically connected to the first detection node; and a second storage diode electrically connected to the second detection node, wherein the first detection structure and the second detection structure are disposed at two opposing vertices of a pixel, respectively, to face each other in a diagonal direction within the pixel.
Inventor(s): Se Chang PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: a memory system includes a memory device including a plurality of memory blocks and a memory controller. the memory controller determines, when a read request for data stored in a first memory block among the plurality of memory blocks is received, whether a dummy read operation on the first memory block is to be performed, based on an erase count value of a second memory block which shares a block word line with the first memory block before a read operation on the first memory block is performed.
20240264757. MEMORY SYSTEM AND OPERATING METHOD THEREOF_simplified_abstract_(sk hynix inc.)
Inventor(s): Duck Joo LEE of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a memory system includes: a memory device including a plurality of memory blocks each including a plurality of pages; and a memory controller configured to allocate, to a meta page among the plurality of pages, a first region including regions configured to store plural pieces of meta data respectively according to types of the plural pieces of meta data, and a second region configured to store additional meta data corresponding to at least one meta data among the plural pieces of meta data is stored, and control the memory device to store the plural pieces of meta data and the additional meta data in the first region and the second region, respectively.
Inventor(s): Oung Sic Cho of Icheon-si (KR) for sk hynix inc., Jong Hoon Oh of Seongnam-si (KR) for sk hynix inc.
IPC Code(s): G06F3/06, G06F11/10
CPC Code(s): G06F3/068
Abstract: a calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.
Inventor(s): Fan ZHANG of San Jose CA (US) for sk hynix inc., Meysam Asadi of San Jose CA (US) for sk hynix inc., Ahmad Golmohammadi of San Jose CA (US) for sk hynix inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: a memory system having a memory block and a memory controller in communication with the memory block. the memory controller is configured to: decode codewords from the memory block, identify failed codewords from the decoded codewords, estimate raw bit errors rbers of the failed codewords, sort failed codewords from a failed sector of the memory block in order from a first set of the failed codewords in the failed sector having a higher probability of being successfully decoded to a second set of the failed codewords in the failed sector having a lower probability of being successfully decoded, and perform a super chip kill sck operation on one of the failed codewords in the first set to produce a recovered codeword.
20240264911. DEVICES USING CHIPLET BASED STORAGE ARCHITECTURES_simplified_abstract_(sk hynix inc.)
Inventor(s): Dong Sop LEE of Icheon-si (KR) for sk hynix inc.
IPC Code(s): G06F11/16, G06F11/10, G06F13/42
CPC Code(s): G06F11/1658
Abstract: a device for implementing a storage architecture includes a front-end chip configured to perform first interfacing with a first device, a plurality of back-end chips configured to perform second interfacing with second devices, and a memory chip disposed to be separated from the front-end chip and the plurality of back-end chips and configured to perform a communication with the front-end chip.
Inventor(s): Eun Soo JANG of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06F12/0895
CPC Code(s): G06F12/0895
Abstract: a memory controller may allocate, to buffer memory, a write data buffer region and a write cache tag (wct) buffer region corresponding to a write command from a host. the memory controller may store write data and wcts for the write data in the write data buffer region and the wct buffer region, respectively.
Inventor(s): Cheol Jon JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Dong Ik KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jun Hyeok CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G06V10/75, G06T7/13, G06V10/56
CPC Code(s): G06V10/751
Abstract: an image signal processor and an image signal processing method are disclosed. the image signal processor includes a half-edge pattern determination unit configured to determine whether a target kernel including a target pixel corresponds to a half-edge pattern, a half-edge pattern matching unit configured to determine directionality of the target kernel based on a half-edge pattern mask in which a highest weight is assigned to a pixel arranged in one direction from the target pixel when the target kernel corresponds to the half-edge pattern, and a pixel interpolation unit configured to interpolate the target pixel using pixel data of a pixel disposed at a position corresponding to the directionality of the target kernel, wherein the half-edge pattern is a pattern in which a region on one side of the edge crossing the kernel is filled with a texture region and a non-texture region.
Inventor(s): Chang Hyun HAN of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Moon Soo SUNG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/08
CPC Code(s): G11C16/08
Abstract: a semiconductor device may include a memory cell array including a first memory string that is connected to a first drain selection line and a second memory string that is connected to a second drain selection line, a control circuit configured to generate a first switch control signal and a second switch control signal based on an address signal, a first switch disposed in a direction corresponding to the first drain selection line and configured to connect a global word line with a local word line or disconnect the global word line from the local word line based on the first switch control signal, and a second switch disposed in a direction corresponding to the second drain selection line and configured to connect the global word line with the local word line or disconnect the global word line from the local word line based on the second switch control signal.
Inventor(s): Yeong Jo MUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/08, G11C16/04, G11C16/10, G11C16/26, G11C16/32
CPC Code(s): G11C16/08
Abstract: a memory device includes: a memory cell array including a cell string including a plurality of memory cells respectively connected between a common source line and a plurality of bit lines; a peripheral circuit for performing an internal operation on the memory cells; and control logic for controlling the peripheral circuit to apply a voltage necessary for the internal operation to word lines connected to the plurality of memory cells. the peripheral circuit includes a pass voltage information generator for generating pass voltage information including a number of clocks input from a time at which a pass voltage is applied to the word lines to a time at which a voltage level of the common source line reaches a predetermined reference level. the control logic includes a pass voltage determiner for determining a pass voltage to be applied to the word lines, based on the pass voltage information.
Inventor(s): Hyung Jin CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chan Hui JEONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/10, G11C16/24, G11C16/34
CPC Code(s): G11C16/102
Abstract: a memory device performs a coarse-program operation and a fine-program operation. during the coarse-program operation, the memory device selectively precharges a bit line to perform a verification. during the fine-program operation, the memory device precharges all bit lines to perform the verification.
Inventor(s): Hyung Jin CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chan Sik PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Chan Hui JEONG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/12, G11C16/24
CPC Code(s): G11C16/12
Abstract: a memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers respectively connected to the plurality of memory cells through a plurality of bit lines and a voltage generating circuit for selectively outputting a program voltage and a verify voltage; and a control circuit configured to control the peripheral circuit to perform a plurality of program loops each including a program voltage apply operation and a verify operation. each of the plurality of page buffers may include: a first latch for storing a verify result according to the verify operation of an nth program loop among the plurality of program loops; and a second latch for storing a verify result according to the verify operation of an (n−1)th program loop among the plurality of program loops.
Inventor(s): Sung Ho PARK of Seoul (KR) for sk hynix inc.
IPC Code(s): G11C16/14, G11C16/04, G11C16/08, G11C16/24
CPC Code(s): G11C16/14
Abstract: a flash memory device includes a control circuit and a cell array including a first memory string including a plurality of first flash memory cells having control gates connected to a plurality of word lines, respectively, and a first bit line selection switch connecting the plurality of first flash memory cells to a first bit line in response to a voltage of a first drain selection line. the control circuit controls a first operation to program a selected flash memory cell with data so that a threshold voltage of the selected flash memory cell becomes greater than a first target threshold voltage and a second operation to erase the selected flash memory cell so that the threshold voltage becomes equal to or smaller than a target threshold voltage, the first target threshold voltage being greater than the target threshold voltage that is set according to the data.
20240265980. MEMORY DEVICE PERFORMING PROGRAM OPERATION_simplified_abstract_(sk hynix inc.)
Inventor(s): Yeong Jo MUN of Gyeonggi-do (KR) for sk hynix inc., Dong Hun KWAK of Gyeonggi-do (KR) for sk hynix inc., Se Chun PARK of Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C11/56, G11C16/04, G11C16/10, G11C16/24
CPC Code(s): G11C16/3427
Abstract: a memory device includes: a memory block including a plurality of memory cells; a peripheral circuit for performing a program operation on selected memory cells among the plurality of memory cells; and a control logic for controlling the program operation of the peripheral circuit. the control logic controls the peripheral circuit to perform a foggy program operation on first memory cells connected to a first word line among the plurality of memory cells, perform a foggy program operation on second memory cells connected to a second word line adjacent to the first word line among the plurality of memory cells, and perform a fine program operation on the first memory cells, based on a target program state of the second memory cells.
Inventor(s): Yeong Jo MUN of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10, G11C16/24
CPC Code(s): G11C16/3427
Abstract: a semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit including a plurality of page buffers each performing an auxiliary verify operation and a main verify operation, which are used to program selected memory cells among the plurality of memory cells; and control logic for controlling the auxiliary verify operation and the main verify operation of the peripheral circuit. during the main verify operation, the control logic controls the peripheral circuit to selectively precharge sensing nodes of the plurality page buffers respectively corresponding to the selected memory cells, based on a result of the auxiliary verify operation.
Inventor(s): Jae Taek KIM of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L23/522, H10B41/10, H10B43/10
CPC Code(s): H01L23/5226
Abstract: a semiconductor device includes a stack disposed over a peripheral circuit. the stack includes alternately stacked insulating layers and sacrificial layers. the semiconductor device also includes a first contact structure penetrating through the stack to connect with the peripheral circuit. the first contact structure includes a protruding part extending outward from a sidewall of the first contact structure. the semiconductor device further includes a second contact structure disposed on the first contact structure. the second contact structure is connected to the protruding part of the first contact structure.
Inventor(s): Nam Jae LEE of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H01L25/18, H01L23/00, H01L25/00, H01L25/065, H10B41/27, H10B41/41, H10B43/27, H10B43/40
CPC Code(s): H01L25/18
Abstract: there are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. the semiconductor memory device includes: a peripheral circuit layer; a bonding structure disposed on the peripheral circuit layer; a channel structure disposed on the bonding structure; a first gate contact structure including a first vertical part penetrating the bonding structure and a first horizontal part intersecting with the first vertical part and extending from the first vertical part; and a first gate conductive pattern in contact with a sidewall of the first horizontal part, the first gate conductive pattern being spaced apart from the first vertical part, the first gate conductive pattern extending to surround the channel structure.
Inventor(s): Cheol Jon JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H04N23/81, H04N23/83
CPC Code(s): H04N23/81
Abstract: an image signal processor, and a method for processing an image signal, include a directionality strength determiner, a half-directional pattern determiner, and a pixel interpolator. the directionality strength determiner divides a target kernel including a target pixel into a plurality of sub-kernels, and generates gradient sum information by calculating directionality strength of each of the plurality of sub-kernels. the half-directional pattern determiner determines whether a half-directional edge pattern is included in each of the sub-kernels in response to the gradient sum information. the pixel interpolator interpolates the target pixel in response to the edge pattern determined by the half-directional pattern determiner.
Inventor(s): Rho Gyu KWAK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Shik JANG of Icheon-si Gyeonggi-do (KR) for sk hynix inc., In Su PARK of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Seok Min CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Won Geun CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc., Jung Dal CHOI of Icheon-si Gyeonggi-do (KR) for sk hynix inc.
IPC Code(s): H10B43/27, H10B41/10, H10B41/27, H10B43/10
CPC Code(s): H10B43/27
Abstract: a semiconductor device includes a first gate structure including a plurality of first conductive layers and a plurality of first insulating layers that are alternately stacked; an isolation insulating layer located in the first gate structure, the isolation insulating layer including a first line portion extending in a first direction, a plurality of first protrusions protruding from the first line portion towards one side of the first line portion in a second direction, and a plurality of second protrusions protruding from the first line portion towards another side of the first line portion in an opposite direction to the first protrusions, wherein the second direction is orthogonal to the first direction; a plurality of first memory patterns, wherein one of the plurality of first memory patterns surrounds one of the plurality of first protrusions; and a plurality of first passivation patterns, wherein one of the plurality of first passivation patterns is located between the first line portion and one of the plurality of first memory patterns.
- SK hynix Inc.
- G01M11/02
- G01R1/073
- G01R31/28
- CPC G01M11/0214
- Sk hynix inc.
- G01S7/481
- G01S17/894
- H01L27/146
- H04N25/77
- CPC G01S7/4816
- G06F3/06
- CPC G06F3/0611
- CPC G06F3/064
- G06F11/10
- CPC G06F3/068
- G06F11/07
- CPC G06F11/1068
- G06F11/16
- G06F13/42
- CPC G06F11/1658
- G06F12/0895
- CPC G06F12/0895
- G06V10/75
- G06T7/13
- G06V10/56
- CPC G06V10/751
- G11C16/08
- CPC G11C16/08
- G11C16/04
- G11C16/10
- G11C16/26
- G11C16/32
- G11C16/24
- G11C16/34
- CPC G11C16/102
- G11C16/12
- CPC G11C16/12
- G11C16/14
- CPC G11C16/14
- G11C11/56
- CPC G11C16/3427
- H01L23/522
- H10B41/10
- H10B43/10
- CPC H01L23/5226
- H01L25/18
- H01L23/00
- H01L25/00
- H01L25/065
- H10B41/27
- H10B41/41
- H10B43/27
- H10B43/40
- CPC H01L25/18
- H04N23/81
- H04N23/83
- CPC H04N23/81
- CPC H10B43/27
