Micron Technology, Inc. patent applications on October 10th, 2024
Patent Applications by Micron Technology, Inc. on October 10th, 2024
Micron Technology, Inc.: 25 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (6), H01L25/065 (3), G11C16/10 (2), H10B12/00 (2), H10B80/00 (2) G06F3/064 (3), G06F3/0619 (1), H10B12/053 (1), H01L33/64 (1), H01L33/0041 (1)
With keywords such as: memory, device, material, region, semiconductor, active, conductive, wordline, cells, and dielectric in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Kang-Yong Kim of Boise ID (US) for micron technology, inc., Yang Lu of Boise ID (US) for micron technology, inc., Wonjun Choi of Boise ID (US) for micron technology, inc., Mark Kalei Hadrick of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: apparatuses and techniques for implementing collision avoidance for bank-shared circuitry that supports usage-based disturbance mitigation are described. a memory device includes bank-shared circuitry coupled to multiple banks. the bank-shared circuitry can support usage-based disturbance mitigation. by using the bank-shared circuitry to service multiple banks, the memory device can have a smaller footprint and can be cheaper to manufacture compared to other memory devices with circuitry dedicated for each bank. to avoid conflicts associated with some sequences of commands that may relate to a same bank or different banks and utilize the bank-shared circuitry, the memory controller applies an appropriate timing offset (or delay) between commands. the timing offset allows the memory device time to finish utilizing the bank-shared circuitry for usage-based disturbance mitigation prior to utilizing the bank-shared circuitry in accordance with a subsequent command.
Inventor(s): Kyungjin Kim of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: disclosed herein are methods, apparatuses and systems related to manage memory blocks. a memory system can track a duration while a memory block remains open for programming operations. when the tracked duration meets or exceeds a corresponding threshold, the memory system can implement an internally commanded programming operation to store predetermined data into an open location that is adjacent to an end of the previously-written data in the memory block.
Inventor(s): Jiangang Wu of Milpitas CA (US) for micron technology, inc., Jung Sheng Hoei of Newark CA (US) for micron technology, inc., Qisong Lin of El Dorado Hills CA (US) for micron technology, inc., Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: a processing device access a command to program data to a page in a block of a memory device. the processing device determines whether the page is a last remaining open page in the block. the processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. the processing device determines the list includes an entry that matches to the block. the entry indicates enablement of the function to apply read level offsets to the block. the processing device disables the function based on determining the page is a last remaining open page in the block. the processing device adds the command to a prioritized queue of commands. the memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.
20240338139. WORDLINE LEAKAGE TEST MANAGEMENT_simplified_abstract_(micron technology, inc.)
Inventor(s): Wai Leong Chin of Singapore (SG) for micron technology, inc., Francis Chee Khai Chew of Singapore (SG) for micron technology, inc., Trismardawi Tanadi of Folsom CA (US) for micron technology, inc., Chun Sum Yeung of San Jose CA (US) for micron technology, inc., Lawrence Dumalag of Folsom CA (US) for micron technology, inc., Ekamdeep Singh of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F3/06, G06F12/06
CPC Code(s): G06F3/064
Abstract: a memory sub-system causing execution of a first wordline leakage test of a first wordline group of a set of wordline groups of a memory block in response to determining a temperature of the memory block is within a threshold temperature range. a first result of the first wordline leakage test is determined. a second wordline leakage test of a second wordline group is caused to be executed and a second result is determined. a determination is made that the first result of the first wordline leakage test of the first wordline group satisfies a first condition. a determination is made that the second result of the second wordline leakage test of the second wordline group satisfies a second condition. in response to satisfaction of the conditions, an action is executed.
Inventor(s): Eyal En Gad of Highland CA (US) for micron technology, inc., Mustafa N. Kaynak of San Diego CA (US) for micron technology, inc., Sivagnanam Parthasarathy of Carlsbad CA (US) for micron technology, inc., Yoav Weinberg of Thornhill (CA) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0655
Abstract: a memory device having a bit-flipping decoder. the decoder having a plurality of circuits operatable to perform parallel computation to decode a codeword according to a plurality of columns of a parity matrix. the decoder is configured to provide columns of the parity matrix for processing in the plurality of circuits in an order where columns processed concurrently by the plurality of circuits in pipeline stages include no more than one parity column of the parity matrix.
20240338149. SCHEDULING FOR MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Chun-Yi Liu of Rancho Cordova CA (US) for micron technology, inc., Ameen D. Akel of Rancho Cordova CA (US) for micron technology, inc., Lance P. Johnson of Saint Paul MN (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for schedule memory are described. specifically, techniques are described for a memory interface between a host system and memory (e.g., a tightly coupled memory). for example, a memory interface block (mib) between the host system and the memory system may schedule access operations performed by the memory system, schedule and perform error control operations, schedule and perform media management operations, as well as schedule and perform other operations. the use of such a mib may enable the improvement of the memory system by reducing latency and increasing efficiency of memory accesses, while reducing impacts on the architecture and design of the host system.
Inventor(s): Marco REDAELLI of Munich (DE) for micron technology, inc.
IPC Code(s): G06F13/42, G06F9/4401, G06F13/40
CPC Code(s): G06F13/4221
Abstract: an embedded system includes a host device that includes a first peripheral component interconnect express (pcie) interface; a non-volatile memory (nvm) device that includes a second pcie interface; and a pcie bus directly coupled to the first pcie interface and the second pcie interface for transmitting direct communications between the host device and the monolithic nvm device.
Inventor(s): Saideep TIKU of Folsom CA (US) for micron technology, inc., Poorna KALE of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06N20/00
CPC Code(s): G06N20/00
Abstract: implementations described herein relate to using machine learning to generate a workload of a storage component. in some implementations, a device may obtain first data relating to commands issued by an operating system of a compute component of a computer system for a storage component of the computer system. the device may obtain second data relating to transactions at the storage component that are responsive to the commands. the device may provide the first data and the second data to train a machine learning model to output generated storage transactions based on an input of operating system commands.
Inventor(s): Joseph Michael McCrate of Boise ID (US) for micron technology, inc., Robert John Gleixner of San Jose CA (US) for micron technology, inc., Hari Giduturi of Folsom CA (US) for micron technology, inc., Ramin Ghodsi of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C11/408, G11C11/4091, G11C13/00
CPC Code(s): G11C11/4087
Abstract: the application relates to an architecture that allows for less precision of demarcation read voltages by combining two physical memory cells into a single logical bit. reciprocal binary values may be written into the two memory cells that make up a memory pair. when activated using bias circuitry and address decoders the memory cell pair creates current paths having currents that may be compared to detect a differential signal. the application is also directed to writing and reading memory cell pairs.
Inventor(s): Yang Lu of Boise ID (US) for micron technology, inc., Kang-Yong Kim of Boise ID (US) for micron technology, inc., Wonjun Choi of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4091, G11C11/4078, G11C11/4096
CPC Code(s): G11C11/4091
Abstract: apparatuses and techniques for implementing a data sense amplifier circuit with a hybrid architecture. with the hybrid architecture, the data sense amplifier circuit includes a first set of amplifiers that are shared by multiple banks and includes a second set of amplifiers with multiple subsets dedicated to different banks. the bank-shared amplifiers support memory operations (e.g., a read operation) across multiple banks. each amplifier within the first set of amplifiers is coupled to at least two banks. the bank-specific amplifiers support usage-based disturbance mitigation for a corresponding bank. each amplifier within the second set of amplifiers is coupled to one of the multiple banks. the bank-shared amplifiers enable the data sense amplifier circuit to have a smaller footprint while the bank-specific amplifiers enable the data sense amplifier circuit to support usage-based disturbance mitigation and avoid conflicts associated with some sequences of commands.
Inventor(s): Sheyang Ning of San Jose CA (US) for micron technology, inc., Lawrence Celso Miranda of San Jose CA (US) for micron technology, inc., Jeffrey S. McNeil of Nampa ID (US) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc., Yeang Meng Hern of Singapore (SG) for micron technology, inc., Lee-eun Yu of San Jose CA (US) for micron technology, inc., Albert Fayrushin of Boise ID (US) for micron technology, inc., Fulvio Rori of Boise ID (US) for micron technology, inc., Justin Bates of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/08, G11C16/04, G11C16/10
CPC Code(s): G11C16/08
Abstract: control logic in a memory device initiates a program operation including a first phase including applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase including applying a set of programming pulses to a wordline associated with one or more memory cells of the memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse. during the first phase of the program operation, a first voltage applied to a drain-side select line (sgd) is adjusted from a first sgd voltage level to a second sgd voltage level.
Inventor(s): Leo Raimondo of Avezzano (IT) for micron technology, inc., Violante Moschiano of Avezzano (IT) for micron technology, inc., Shyam Sunder Raghunathan of Singapore (SG) for micron technology, inc., Akira Goda of Tokyo (JP) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10
CPC Code(s): G11C16/3427
Abstract: control logic in a memory device initiates a program operation on a memory array comprising a top deck and bottom deck. during a seeding phase of the program operation, the control logic causes a first positive voltage to be applied to a first plurality of wordlines of the memory array, wherein the first plurality of wordlines is associated with memory cells in the bottom deck of the memory array that are in a programmed state, and causes a ground voltage to be applied to a second plurality of wordlines of the memory array, wherein the second plurality of wordlines is associated with memory cells in the top deck of the memory array. at an end of the seeding phase of the program operation, the control logic electrically separates the top deck from the bottom deck and causes a program voltage to be applied to a selected wordline of the memory array during an inhibit phase of the program operation, wherein the selected wordline is associated with respective memory cells in the top deck of the memory array.
20240339170. INTERRUPTING A MEMORY BUILT-IN SELF-TEST_simplified_abstract_(micron technology, inc.)
Inventor(s): Scott E. SCHAEFER of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/46, G11C29/42, G11C29/44
CPC Code(s): G11C29/46
Abstract: implementations described herein relate to interrupting a memory built-in self-test. a memory device may read one or more bits, associated with a memory built-in self-test, that are stored in a mode register of the memory device. the memory device may identify, based on the one or more bits, that the memory built-in self-test is to be interrupted while the memory built-in self-test is being performed using a test mode. the memory device may be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode but may not be permitted to interrupt the memory built-in self-test while the memory built-in self-test is being performed using a repair mode. the memory device may interrupt the memory built-in self-test while the memory built-in self-test is being performed using the test mode.
Inventor(s): Yugang Yu of Folsom CA (US) for micron technology, inc., Chun Sum Yeung of San Jose CA (US) for micron technology, inc., Pitamber Shukla of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C29/52, G11C29/02
CPC Code(s): G11C29/52
Abstract: aspects of the present disclosure are directed to a memory sub-system using a block family error avoidance (bfea) scan to adjust read voltages. three-level cell (tlc) memory stores three bits per cell. due to variances in manufacturing and degradation over time, the actual voltages stored in the memory cells deviate from the target voltages. as a result, the comparisons between the read voltages and the stored voltages may generate erroneous results. a bfea scan may be based on a single wordline and single page type. however, determining a single threshold voltage shift to apply to all read voltages may not compensate for all causes of voltage shifting. accordingly, a bfea scan may use multiple wordlines (e.g., one for each page) and determine different voltage offset values for each page. as a result, the accuracy of the read voltage applied is increased and the bit error rate (ber) is reduced.
Inventor(s): Darwin A. Clampitt of Wilder ID (US) for micron technology, inc., John D. Hopkins of Meridian ID (US) for micron technology, inc., Madison D. Drake of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L21/768, H01L23/532, H01L23/535, H10B41/27, H10B43/27
CPC Code(s): H01L21/7682
Abstract: a microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, strings of memory cells vertically extending through the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, a conductive contact structure vertically overlying and in electrical communication with the channel material of a string of memory cells of the strings of memory cells, and a void laterally neighboring the conductive contact structure, the conductive contact structure separated from a laterally neighboring conductive contact structure by the void, a dielectric material, and an additional void laterally neighboring the laterally neighboring conductive contact structure. related memory devices, electronic systems, and methods are also described.
Inventor(s): William M. Hiatt of Eagle ID (US) for micron technology, inc., Ross S. Dando of Nampa ID (US) for micron technology, inc.
IPC Code(s): H01L21/768, H01L23/48, H01L23/498, H01L23/538
CPC Code(s): H01L21/76898
Abstract: methods for forming interconnects in microfeature workpieces, and microfeature workpieces having such interconnects are disclosed herein. the microfeature workpieces may have a terminal and a substrate with a first side carrying the terminal and a second side opposite the first side. in one embodiment, a method includes (a) constructing an electrically conductive interconnect extending from the terminal to at least an intermediate depth in the substrate with the interconnect electrically connected to the terminal, and (b) removing material from the second side of the substrate so that a portion of the interconnect projects from the substrate.
Inventor(s): Bharat Bhushan of Taichung (TW) for micron technology, inc., Nevil N. Gajera of Meridian ID (US) for micron technology, inc., Akshay N. Singh of Boise ID (US) for micron technology, inc., Kunal R. Parekh of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L23/00, H01L23/31, H01L23/48, H01L25/00, H10B80/00
CPC Code(s): H01L25/0652
Abstract: a semiconductor device with a through dielectric via is disclosed. the semiconductor device assembly can include a semiconductor die and multiple stacks of semiconductor dies coupled with the semiconductor die at different lateral locations. dielectric material can be disposed at the semiconductor die between the multiple stacks of semiconductor dies. the through dielectric via can extend entirely through the dielectric material to the semiconductor die such that the through dielectric via couples with circuitry at the semiconductor die. in this way, the through dielectric via can provide power to the semiconductor die (e.g., exclusive of the multiple stacks of semiconductor dies).
Inventor(s): Hyunsuk Chun of Boise ID (US) for micron technology, inc., Xiaopeng Qu of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L21/56, H01L23/31, H01L23/373, H01L25/00
CPC Code(s): H01L25/0657
Abstract: semiconductor device assemblies are provided with one or more layers of thermally conductive material disposed between adjacent semiconductor dies in a vertical stack. the thermally conductive material can be configured to conduct heat generated by one or more of the semiconductor dies in laterally outward towards an outer edge of the assembly. the layer of thermally conductive material can comprise one or more allotropes of carbon, such as diamond, graphene, graphite, carbon nanotubes, or a combination thereof. the layer of thermally conductive material can be provided via deposition (e.g., sputtering, pvd, cvd, or ald), or via adhering a film comprising the layer of thermally conductive material to one or more of the semiconductor dies.
Inventor(s): TOMOHIRO KITANI of Higashihiroshima (JP) for micron technology, inc.
IPC Code(s): H01L27/02, H10B12/00
CPC Code(s): H01L27/0207
Abstract: an apparatus includes: a semiconductor substrate: active regions in the semiconductor substrate, each of the active regions surrounded by a shallow trench isolation and each divided, at least in part, into a first active area and a second active area having a channel area therebetween; first wirings over the plurality of active regions, each of the first wirings coupled to the first active areas of corresponding ones of the active regions; and second wirings over the active regions, each of the second wirings coupled to the second active areas of associated ones of the active regions. each of the active regions has a longer side in a first direction, each of the first wirings extends in a second direction different from the first direction and each of the second wirings extends in a third direction different from each of the first direction and the second direction.
Inventor(s): Quang NGUYEN of Boise ID (US) for micron technology, inc., Christopher GLANCEY of Boise ID (US) for micron technology, inc., Koustav SINHA of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/06, H01L21/78, H01L23/00, H01L25/065, H10B80/00
CPC Code(s): H01L29/0657
Abstract: implementations described herein relate to various semiconductor device assemblies. in some implementations, a semiconductor die includes a first main face and an opposing second main face, the first main face and the second main face being spaced apart from one another in a direction. the semiconductor die may include a plurality of side faces disposed substantially perpendicular to the first main face and the second main face, the plurality of side faces extending between the first main face and the second main face in the direction. the semiconductor die may include one of a first rounded edge or a first chamfered edge, the one of the first rounded edge or the first chamfered edge connecting at least one side face, of the plurality of side faces, to the first main face.
Inventor(s): Witold Kula of Gilroy CA (US) for micron technology, inc., Gurtej S. Sandhu of Boise ID (US) for micron technology, inc., John A. Smythe of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L29/786, H01L21/02, H01L29/24, H01L29/66, H10B99/00
CPC Code(s): H01L29/78642
Abstract: an apparatus including an array of memory cells comprising transistors is disclosed. one or more of the transistors comprise a crystalline material extending substantially transverse to a base material. a gate dielectric material is adjacent to the crystalline material. a two-dimensional material of a channel region directly intervenes between the gate dielectric material and the crystalline material. the gate dielectric material overlies additional portions of the two-dimensional material of the channel region. one or more gates are adjacent to the gate dielectric material. an electronic device is also disclosed comprising one or more of the transistors. the one or more of the transistors comprise a channel region, a gate dielectric region adjacent to the channel region, and one or more gates adjacent to the gate dielectric region. the channel region comprises opposing sidewalls separated by a pillar structure and substantially perpendicular to a base material.
Inventor(s): Martin F. Schubert of Mountain View CA (US) for micron technology, inc., Vladimir Odnoblyudov of Eagle ID (US) for micron technology, inc.
IPC Code(s): H01L33/00, F21V23/00, F21Y115/10, H01L27/15, H01L33/06, H01L33/32, H01L33/38, H05B44/00, H05B45/00
CPC Code(s): H01L33/0041
Abstract: various embodiments of solid state transducer (“sst”) devices are disclosed. in several embodiments, a light emitter device includes a metal-oxide-semiconductor (mos) capacitor, an active region operably coupled to the mos capacitor, and a bulk semiconductor material operably coupled to the active region. the active region can include at least one quantum well configured to store first charge carriers under a first bias. the bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits uv light.
Inventor(s): Kevin Tetz of Boise ID (US) for micron technology, inc., Charles M. Watkins of Eagle ID (US) for micron technology, inc.
IPC Code(s): H01L33/64, H01L25/075, H01L33/44, H01L33/50, H01L33/52
CPC Code(s): H01L33/64
Abstract: solid state lighting devices and associated methods of thermal sinking are described below. in one embodiment, a light emitting diode (led) device includes a heat sink, an led die thermally coupled to the heat sink, and a phosphor spaced apart from the led die. the led device also includes a heat conduction path in direct contact with both the phosphor and the heat sink. the heat conduction path is configured to conduct heat from the phosphor to the heat sink.
Inventor(s): Babak Tahmouresilerd of Boise ID (US) for micron technology, inc., Ramaswamy Ishwar Venkatanarayanan of Boise ID (US) for micron technology, inc., Don Koun Lee of Boise ID (US) for micron technology, inc., Purnima Narayanan of Fremont CA (US) for micron technology, inc., Sanjeev Sapra of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/053
Abstract: methods, systems, and devices for wordline recess formation and resulting structures are described. in some instances, aspects of a memory device may be formed using a wet etching process. for example, a wet etching process may be used to remove (e.g., etch) one or more materials (e.g., nitrides) when forming wordlines. the wet etching process may include depositing a first resist material and a second resist material to selectively remove (e.g., etch) different portions of the nitride material. such processes may result in gate oxides of the memory device being relatively uniform in shape.
Inventor(s): Shuangqiang Luo of Boise ID (US) for micron technology, inc., Indra V. Chary of Boise ID (US) for micron technology, inc., Kar Wui Thong of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H10B41/27
CPC Code(s): H10B43/27
Abstract: memory circuitry comprising strings of memory cells comprises vertically-alternating insulative tiers and conductive tiers that extend from a memory-array region into a stair-step region across an intermediate region that is between the memory-array region and the stair-step region. the insulative tiers and the conductive tiers comprise memory blocks upper portions of which individually comprise sub-blocks. sub-block trenches are in the upper portions individually between immediately-laterally-adjacent of the sub-blocks. strings of memory cells in the memory-array region comprise channel-material strings that extend through the insulative tiers and the conductive tiers in the memory blocks and in the sub-blocks. the sub-block trenches in the memory-array region, in the intermediate region, and in the stair-step region individually have a top. the top of individual of the sub-block trenches in the stair-step region has a narrowest-width that is larger than a narrowest-width of the top of the individual sub-block trenches in the intermediate region. the narrowest-width of the top of the individual sub-block trenches in the intermediate region is larger than a narrowest-width of the top of the individual sub-block trenches in the memory-array region. other embodiments, including method, are disclosed.
Micron Technology, Inc. patent applications on October 10th, 2024
- Micron Technology, Inc.
- G06F3/06
- CPC G06F3/0619
- Micron technology, inc.
- CPC G06F3/064
- G06F12/06
- CPC G06F3/0655
- CPC G06F3/0659
- G06F13/42
- G06F9/4401
- G06F13/40
- CPC G06F13/4221
- G06N20/00
- CPC G06N20/00
- G11C11/408
- G11C11/4091
- G11C13/00
- CPC G11C11/4087
- G11C11/4078
- G11C11/4096
- CPC G11C11/4091
- G11C16/08
- G11C16/04
- G11C16/10
- CPC G11C16/08
- G11C16/34
- CPC G11C16/3427
- G11C29/46
- G11C29/42
- G11C29/44
- CPC G11C29/46
- G11C29/52
- G11C29/02
- CPC G11C29/52
- H01L21/768
- H01L23/532
- H01L23/535
- H10B41/27
- H10B43/27
- CPC H01L21/7682
- H01L23/48
- H01L23/498
- H01L23/538
- CPC H01L21/76898
- H01L25/065
- H01L23/00
- H01L23/31
- H01L25/00
- H10B80/00
- CPC H01L25/0652
- H01L21/56
- H01L23/373
- CPC H01L25/0657
- H01L27/02
- H10B12/00
- CPC H01L27/0207
- H01L29/06
- H01L21/78
- CPC H01L29/0657
- H01L29/786
- H01L21/02
- H01L29/24
- H01L29/66
- H10B99/00
- CPC H01L29/78642
- H01L33/00
- F21V23/00
- F21Y115/10
- H01L27/15
- H01L33/06
- H01L33/32
- H01L33/38
- H05B44/00
- H05B45/00
- CPC H01L33/0041
- H01L33/64
- H01L25/075
- H01L33/44
- H01L33/50
- H01L33/52
- CPC H01L33/64
- CPC H10B12/053
- CPC H10B43/27
