Micron Technology, Inc. patent applications on August 29th, 2024
Patent Applications by Micron Technology, Inc. on August 29th, 2024
Micron Technology, Inc.: 59 patent applications
Micron Technology, Inc. has applied for patents in the areas of G06F3/06 (8), G06F12/02 (6), G11C16/04 (5), G11C11/408 (4), G06F11/10 (4) G06F11/1068 (4), G11C11/4091 (3), G06F12/0246 (3), G11C16/0483 (2), G06F1/3225 (2)
With keywords such as: memory, device, data, access, devices, described, bits, voltage, based, and systems in patent application abstracts.
Patent Applications by Micron Technology, Inc.
Inventor(s): Jean-Sebastien Materne Lehn of Boise ID (US) for micron technology, inc.
IPC Code(s): C23C16/455
CPC Code(s): C23C16/45553
Abstract: methods, systems, and devices for atomic layer deposition using tin-based or germanium-based precursors are described. for instance, a device may react a first precursor with a material to form a first compound including a first element on the material, where the first compound includes at least one of a group xiii, group xiv, or group xv element. additionally, the device may react a second precursor with the first compound to form a second compound on the base material, where the second precursor has the chemical formula b-c(1)-d(1), b-c(1)-c(1)-d(1), b-c(2)-d(1)d(2), bd(3)-c(2)-c(2)-d(1)d(2), b-c(3)-d(1)d(2)d(3), or bd(4)d(5)-c(3)-c(3)-d(1)d(2)d(3), where each of b, d(1), d(2), d(3), d(4), and d(5) are a respective moiety that independently includes at least one of germanium, tin, or silicon, and where c(1) comprises tellurium, sulfur, or selenium, where c(2) comprises antimony, arsenic, and phosphorous, and where c(3) comprises silicon, germanium, or tin.
20240288480. CAPACITOR TEST_simplified_abstract_(micron technology, inc.)
Inventor(s): Marco REDAELLI of Munich (DE) for micron technology, inc.
IPC Code(s): G01R31/01, G01R27/26
CPC Code(s): G01R31/016
Abstract: implementations described herein relate to a capacitor test. in some implementations, a system may include a memory device, one or more capacitors located externally to the memory device, and one or more components configured to initiate a capacitor test for the one or more capacitors. the one or more components may be configured to perform an iteration of the capacitor test for the one or more capacitors, wherein performing the iteration of the capacitor test comprises waiting a time period, increasing a discharge time, reading a counter associated with the capacitor test, and determining whether a value of the counter has increased. the one or more components may be configured to perform another iteration of the capacitor test or terminate the capacitor test based on determining whether the value of the counter has increased.
Inventor(s): Michael Richard Spica of Eagle ID (US) for micron technology, inc.
IPC Code(s): G01R31/3185, G01R31/28, G01R31/317
CPC Code(s): G01R31/318597
Abstract: a method performed by automated test equipment (ate) includes power cycling a solid state drive (ssd) device under test by the ate, wherein the ssd device includes a memory controller integrated circuit (ic) attached to a printed circuit board (pcb) having a pcb interface; communicating one or more signals between the ate and the memory controller ic using the pcb interface in a normal system mode; sending a command to cause the memory controller ic to place the pcb interface in a boundary scan mode; remapping a portion of pins of the pcb interface to a boundary scan interface; and communicating one or more boundary scan signals between the ate and the memory controller ic using the remapped portion of pins of the pcb interface in the boundary scan mode.
Inventor(s): Liang Yu of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Giuseppe Cariello of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/30
CPC Code(s): G06F1/3225
Abstract: methods, systems, and devices for power arbitration for systems of electronic components are described. a system may include a power source, a signaling conductor coupled with a voltage source, and a set of electronic components. one or more of the electronic components may include respective circuitry coupled with the power source and a respective switching component (e.g., a transistor) coupled with the signaling conductor. in some implementations, an electronic component of the set may be configured to determine an operation of its respective circuitry that is associated with a power consumption from the power source. based on such a determination, the electronic component may switch its respective switching component in accordance with an identifier associated with the electronic component, and determine whether to perform the operation based on monitoring a signal level of the signaling conductor during the switching.
20240288925. MEMORY EXPANSION CARD_simplified_abstract_(micron technology, inc.)
Inventor(s): Brent Keeth of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F1/3225, G06F13/16, G06F13/40
CPC Code(s): G06F1/3225
Abstract: the present disclosure includes apparatuses and methods related to a memory expansion card suitable for, relative to other memory solutions, a high-speed interface and low power consumption. the memory expansion card can have on-die error correction code (ecc) circuitry and, in some examples, additional on-board circuitry, components, or capability to manage, relative to other memory solutions, a large number of volatile or non-volatile memory devices. a memory expansion card may have a controller with a host interface capable of using or defined according to a quantity of bits (i.e., a bit width), which may be eight bits. the controller may coupled to memory devices via several channels, and each channel may have the bit width of the interface.
Inventor(s): Luca Porzio of Casalnuovo (NA) (IT) for micron technology, inc., Daniela Ruggeri of Torre del Greco (NA) (IT) for micron technology, inc., Dionisio Minopoli of Frattamaggiore (NA) (IT) for micron technology, inc., Paolo Amato of Treviglio (BG) (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0611
Abstract: methods, systems, and devices for techniques for efficient memory system programming are described. a memory system may operate in a programming mode to be programmed with data at various stages of being implemented into a system. in some examples, the memory system may write data according to a programming command sequence, including a first command indicating multiple logical block address (lba) ranges of the memory system. the memory system may receive multiple second commands that each include data associated with respective lba ranges and may write, for each respective lba range, data to physical addresses of the memory system. alternatively, the memory system may write a value to a register indicating a total quantity of lbas associated with writing data while operating in the programming mode. the memory system may decrement the value of the register in response to writing data to the memory system.
Inventor(s): Nitul Gohain of Bangalore (IN) for micron technology, inc., Nicola Colella of Capodrise (CE) (IT) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: methods, systems, and devices for data separation configurations for memory systems are described. a memory system may store one or more characteristics of data, which may be utilized to improve performance associated with transferring the data between blocks of memory cells. for example, a memory system may be configured to evaluate whether to separate data in one or more transfer operations based on the characteristics of the data. some transfer configurations may include transferring data independent of characteristics of the data and some other transfer configurations may include transferring data based on characteristics of the data. in some examples, a transfer configuration may include transferring data associated with a relatively longer validity duration characteristic before transferring data associated with a relatively shorter validity duration characteristic, which may include transferring data associated with different validity duration characteristics to the same target block or to different target blocks.
Inventor(s): Aswin Thiruvengadam of Folsom CA (US) for micron technology, inc., Vamsi Pavan Rayaprolu of Santa Clara CA (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0619
Abstract: systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. the processing device can perform operations including running sample data through each of a set of error-handling operations performed on data residing in a segment of the memory device in an existing order; and determining an optimized order of the set of error-handling operations based on probability data and latency data, wherein the probability data is associated with a result of running the sample data, and wherein the optimized order comprises an adjustment to an order of one or more error-handling operations of the set of error-handling operations in the existing order.
Inventor(s): Gianluca COPPOLA of Liveri (IT) for micron technology, inc., Steffen BUCH of Taufkirchen (DE) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0632
Abstract: in some implementations, a memory device may receive, from a host device, a hardware reset signal. the memory device may determine that a level associated with the hardware reset signal satisfies a threshold for a period of time. the memory device may determine, based on the hardware reset signal satisfying the threshold for the period of time, that the host device is expected to power down the memory device. the memory device may complete an ongoing memory operation within a remaining time period based on the determination that the host device is expected to power down the memory device.
20240289042. BLOCK REPLACEMENT USING COMBINED BLOCKS_simplified_abstract_(micron technology, inc.)
Inventor(s): Nikhil Birgade of Hyderabad (IN) for micron technology, inc., Uday Bhasker V. Vudugandla of Hyderabad (IN) for micron technology, inc., Mani Raghavendra Aravapalli of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/064
Abstract: methods, systems, and devices for block replacement using combined blocks are described. a memory system may receive a command to perform an access operation on a block of the memory system. the memory system may determine whether a block pool includes a second block configured to replace the block based on a failure to perform the access operation. the memory system may generate a combined block for replacing the block based on determining an absence of the second block in the block pool. the combined block may be generated by combining two half good blocks (hgbs) in a same plane of the memory system as the block. in some cases, a second block pool may be generated and the combined block may be stored to the second block pool. the memory system may select the combined block from the second block pool and replace the block with the combined block.
20240289050. WRITE BOOSTER BUFFER AND HIBERNATE_simplified_abstract_(micron technology, inc.)
Inventor(s): Luca Porzio of Casalnuovo (IT) for micron technology, inc., Deping He of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0656
Abstract: methods, systems, and devices for write booster buffer and hibernate are described. the memory system may initiate a first operation to enter a first power mode having a lower power consumption than a second power mode. in some cases, the memory system may determine whether a quantity of data stored in a buffer of single-level cells associated with write booster information satisfies a threshold based on initiating the first operation. the memory system may determine whether to perform a second operation to transfer the quantity of data stored in the buffer of single-level cells to a portion of memory comprising multiple level cells based on determining whether the quantity of data satisfies the threshold. the memory system may enter the first power mode based on determining to perform the second operation to transfer the quantity of data from the buffer to the portion of memory.
Inventor(s): Jonathan S. Parry of Boise ID (US) for micron technology, inc., David Aaron Palmer of Boise ID (US) for micron technology, inc., Reshmi Basu of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for ordering entries of an input command queue are described. a memory system may include an interface (e.g., a host interface) that includes a queue (e.g., an input command queue). the host interface may receive commands from a host system, and the commands may be inserted into the input command queue in an order they are received. in some examples, the memory system may determine a range of logical block addresses (lbas) associated with one or more entries in the input command queue. the memory system may order (e.g., reorder) the commands such that the respective lba ranges are contiguous.
Inventor(s): Giuseppe Cariello of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F3/06
CPC Code(s): G06F3/0659
Abstract: methods, systems, and devices for data type identification schemes for memory systems are described. a memory system may transfer data from one block of memory cells to another based on an indication of a characteristic of the data, such as a data type, a validity characteristic, or a data temperature. for example, data associated with a relatively longer validity duration may be prioritized for transfer to another block prior to data associated with a relatively shorter validity duration. an indication of a characteristic of the data may be received from a host system, and may be stored at the memory system in an entry of a physical-to-logical (p2l) table, or in accompanying metadata, or both. an indication of a data characteristic (e.g., a stream id) may be maintained with the data throughout a validity duration of the data (e.g., through multiple flush or other transfer operations).
20240289159. MEMORY DEVICE VIRTUALIZATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Gaurav SINHA of Unterschleißheim (DE) for micron technology, inc., Marco REDAELLI of Munich (DE) for micron technology, inc.
IPC Code(s): G06F9/455, G06F8/61
CPC Code(s): G06F9/45558
Abstract: implementations described herein relate to memory device virtualization. in some implementations, a memory device may perform a boot-up of the memory device and may receive configuration information associated with a single root input-output virtualization for the memory device. the memory device may store the configuration information in a memory of the memory device. the memory device may perform a subsequent boot-up of the memory device. the memory device may retrieve the configuration information from the memory of the memory device after performing the subsequent boot-up of the memory device. the memory device may initiate one or more virtual functions associated with the single root input-output virtualization based on retrieving the configuration information from the memory of the memory device.
Inventor(s): Christophe Vincent Antoine Laurent of Agrate Brianza (MB) (IT) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1068
Abstract: in some aspects, the techniques described herein relate to a method including: generating quantized knuth (qk) index bits for a codeword, the qk index bits selected from a list of qk bits; computing a parity portion based on the payload and the qk index bits; combining the payload, parity portion, and the qk index bits to form a codeword; and writing the codeword to a memory device.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/10
CPC Code(s): G06F11/1068
Abstract: apparatuses, systems, and methods for variable input error correction code (ecc) circuits. different modes of a memory device may involve different numbers of bits of information (e.g., data and/or metadata) being accessed. an ecc input circuit receives the variable number of bits of information and provides a fixed number of input bits. an ecc engine uses the input bits to generate parity (during a write) or to locate errors (during a read). the number of input bits may be based on a number of inputs of the ecc engine. the ecc input circuit may generate filler bits to add to the bits of information to generate the input bits.
Inventor(s): David Ebsen of Minnetonka MN (US) for micron technology, inc., Kishore Kumar Muchherla of San Jose CA (US) for micron technology, inc., James Fitzpatrick of Laguna Niguel CA (US) for micron technology, inc., Dung V. Nguyen of San Jose CA (US) for micron technology, inc., Kevin R. Brandt of Boise ID (US) for micron technology, inc., Vikas Rana of Pehowa (IN) for micron technology, inc., William Richard Akin of Morgan Hill CA (US) for micron technology, inc.
IPC Code(s): G06F11/10, G06F13/16
CPC Code(s): G06F11/1068
Abstract: data is read from a set of memory cells of a memory device to a buffer of the memory device. one or more bits in error in the data stored by the buffer are corrected by a decoder of the memory device. the decoder corrects the one or more bits in error by decoding the data stored by the buffer. the decoding of the data results in corrected data. an encoder of the memory device encodes the corrected data and the encoded corrected data is programmed to the set of memory cells.
Inventor(s): Steffen Buch of Munich (DE) for micron technology, inc., Thomas Hein of Munich (DE) for micron technology, inc.
IPC Code(s): G06F11/10, G06F11/07
CPC Code(s): G06F11/1068
Abstract: methods, systems, and devices for memory operations are described. a first code for detecting one or more errors in a first set of bits of data and a second code for detecting one or more errors in a second set of bits of data may be generated. the first set of bits and the second set of bits may be transmitted over a channel between a memory device and a host device in an interleaved pattern. the first code and the second code may also be transmitted over the channel. the first set of bits and the second set of bits may be deinterleaved by the receiving device. the first set of bits and the second set of bits may also be processed by the receiving device using the first code and the second code.
Inventor(s): Larry J. Koudele of Erie CO (US) for micron technology, inc., Bruce A. Liikanen of Berthoud CO (US) for micron technology, inc.
IPC Code(s): G06F11/14, G06F11/07, G11C11/56, G11C16/26, G11C29/02, G11C29/44, G11C29/52
CPC Code(s): G06F11/142
Abstract: a system includes a memory array; and a processing device coupled to the memory array. the processing device may be configured to iteratively adjust an active processing level, wherein, for each iteration, the processing device is configured to: determine a first set of read results corresponding to the active processing level, determine a second set of read results based on an offset processing level different than the active processing level, and incrementally adjust the active processing level based on a comparison of the first and the second read results.
Inventor(s): Nitul Gohain of Bangalore (IN) for micron technology, inc., Jameer Mulani of Bangalore (IN) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F11/14
CPC Code(s): G06F11/1469
Abstract: methods, systems, and devices for efficient data management for memory system error handling are described. if a new data transfer is desired between the controller and a memory device when the latches are full, the controller may obtain data that has been loaded in one of the latches, temporarily store that data in a buffer, and overwrite the latch with the new data associated with the new data transfer. after the controller is finished working with the new data now stored in the latch, the controller may restore the data from the buffer to the latch so the prior data transfer may continue. this may prevent loss of data or reduce the quantity of data that is temporarily lost from latches and needs to be re-transferred when the latches are full.
20240289242. INPUT/OUTPUT (I/O) COMPONENT TESTING_simplified_abstract_(micron technology, inc.)
Inventor(s): Ming-ta Hsieh of Woodbury MN (US) for micron technology, inc., Taylor Loftsgaarden of Eden Prairie MN (US) for micron technology, inc.
IPC Code(s): G06F11/263, G06F11/22
CPC Code(s): G06F11/263
Abstract: i/o components can be tested in a collective manner. i/o components can be linked such that a test signal is transmitted through the i/o components (e.g., by being propagated from one i/o component to another i/o component) such that the i/o components are tested via a single transmission of the test signal.
Inventor(s): Sujeet Ayyapureddi of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02
CPC Code(s): G06F12/0223
Abstract: apparatuses, systems, and methods for adjustable write timing. memory devices include a first data terminal and a second data terminal. as part of an access operation a first set of data and a first set of metadata may be sent/received across the first terminal and a second set of data and a second set of metadata may be sent/received across the second terminal. when a first setting is enabled, the first set of metadata may be stored in a first location and the second set of metadata may be stored in a second location in the memory array, such as a first and second column plane. the two locations may be remote from each other. when disabled, the metadata may be stored in a single location. a second setting may be used to adjust a write delay to account for different timing when the first setting is enabled vs disabled.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F9/54, G06F12/0815
CPC Code(s): G06F12/0246
Abstract: memory sub-systems configured to run file system managers and to provide file services via memory services. for example, a connection from a memory sub-system to the host system can support both a cache-coherent memory access protocol to a memory device attached by the memory sub-system to the host system and a storage access protocol to a storage device attached by the memory sub-system to the host system. a messaging channel through the memory device can be used for an operating system running in the host system to communicate with a file system manager running in the memory sub-system to access the file system. for example, a hypertext transfer protocol (http) representational state transfer (rest) application programming interface (api) can be implemented for the host system to access the file system in the memory sub-system.
Inventor(s): Luca Bert of San Jose CA (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/06, G06F13/42
CPC Code(s): G06F12/0246
Abstract: memory sub-systems configured to manage storage locations of files for a host system. for example, a connection from a memory sub-system to the host system can support both a cache-coherent memory access protocol to a memory device implemented in the storage capacity of the memory sub-system and a storage access protocol. the memory sub-system can maintain, and share with the host system via the memory device, a medium map configured to identify, for a file stored in the memory sub-system, memory addresses usable for the host system to access locations in the file over the connection using the cache-coherent memory access protocol, and/or logical block addresses usable for the host system to access blocks of the files over the connection using the storage access protocol.
Inventor(s): Ritesh Tiwari of Bangalore (IN) for micron technology, inc., Giuseppe Cariello of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/02, G06F12/0882
CPC Code(s): G06F12/0246
Abstract: methods, systems, and devices for systems and techniques for updating logical-to-physical (l2p) mappings are described. a memory system may support improved change log entries that supports a change log entry to indicate updated l2p mapping information for multiple data chunks, thus increasing the amount of data indicated by the change log before it becomes full. one change log entry may be used to indicate updated l2p information for multiple sequential data chunks. for example, the memory system may write data to a set of contiguous data chunks of a non-volatile memory device. the memory system may write a change log entry to a change log that includes updated l2p mapping information for the set of data chunks by including at least a first indication of a virtual block that includes the data chunks and a second indication of the quantity of data chunks in the set.
Inventor(s): Stephen Hanna of Fort Collins CO (US) for micron technology, inc.
IPC Code(s): G06F12/1009, G06F12/02
CPC Code(s): G06F12/1009
Abstract: methods, systems, and devices for creating high density logical to physical mapping are described. a memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. a memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. the memory device may generate and store a set of compressed entries in a macro level of the mapping information. when the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.
20240289283. MEMORY ACCESS DETERMINATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Richard C. Murphy of Boise ID (US) for micron technology, inc.
IPC Code(s): G06F12/14, G06F9/455
CPC Code(s): G06F12/1491
Abstract: apparatuses and methods related to computer memory access determination are described. a command can be received at a memory system (e.g., a system with or exploiting dram). the command can comprise a memory operation and a plurality of privilege bits. the privilege level or a memory address that is associated with the memory operation can be identified. the privilege level can correspond to the memory address can describe a privilege level that can access the memory address. a determination can be made as to whether the memory operation, or the application requesting certain data or prompting corresponding instructions, is entitled to access to the memory address using the plurality of privilege bits and the privilege level. responsive to determining that the memory operation has access to the memory address, the memory operation can be processed.
20240289597. TRANSFORMER NEURAL NETWORK IN MEMORY_simplified_abstract_(micron technology, inc.)
Inventor(s): Jing Gong of Boise ID (US) for micron technology, inc., Stewart R. Watson of Boise ID (US) for micron technology, inc., Dmitry Vengertsev of Boise ID (US) for micron technology, inc., Ameya Parab of Millburn NJ (US) for micron technology, inc.
IPC Code(s): G06N3/049, G06N3/065, G06N3/084, G06N5/046, G11C13/00, H03M1/12
CPC Code(s): G06N3/049
Abstract: apparatuses and methods can be related to implementing a transformer neural network in a memory. a transformer neural network can be implemented utilizing a resistive memory array. the memory array can comprise programmable memory cells that can be programed and used to store weights of the transformer neural network and perform operations consistent with the transformer neural network.
20240289634. TRUST BASED FEDERATED LEARNING_simplified_abstract_(micron technology, inc.)
Inventor(s): Shashank Bangalore Lakshman of Folsom CA (US) for micron technology, inc., Pavana Prakash of Houston TX (US) for micron technology, inc., Poorna Kale of Folsom CA (US) for micron technology, inc.
IPC Code(s): G06N3/098, G06N3/04
CPC Code(s): G06N3/098
Abstract: apparatuses and methods related to federated learning are described. a host system can, responsive to a valid trust signal from a first local device, communicate a global model and a global loss value to the local device. the host system can receive a local loss value from the local device. the local loss value can be based on execution of a local version of the global model, generated by the local device, on a local test dataset by the local device. the host system can analyze the local loss value based on quantities of training samples and test samples. responsive to the local loss value being more preferred than the global loss value, the host system can receive the local version of the global model from the local device, update the global model, and communicate the updated global model to the local device and to another local device.
Inventor(s): Youngkwon Jo of Meridian ID (US) for micron technology, inc.
IPC Code(s): G11C7/22, G11C7/10
CPC Code(s): G11C7/222
Abstract: systems and methods of the present disclosure may involve a memory device that includes a command path. the command path may include a command decoder. the memory device may also include a clock path. the clock path may include a multiplexer coupled to the command path via one or more flip-flops. by including the multiplexer in the clock path, a reduced amount of processing bottleneck may occur in the command decoder.
20240290373. GENERATING ACCESS LINE VOLTAGES_simplified_abstract_(micron technology, inc.)
Inventor(s): Martin Brox of Munich (DE) for micron technology, inc., C. Omar Benitez of Meridian ID (US) for micron technology, inc., Johnathan L. Gossi of Boise ID (US) for micron technology, inc., Christopher John Kawamura of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/408, G11C5/14, G11C11/22, G11C11/4094
CPC Code(s): G11C11/4085
Abstract: methods, systems, and devices for techniques for generating access line voltages are described. a system may use a first voltage supply and a second voltage supply that is configured to supply a lower voltage than the first voltage supply. the system may activate a first circuit to couple a node with the first voltage supply so that a first voltage develops on the node from the first voltage supply. the system may activate a second circuit to couple the node with the second voltage supply so that a second voltage that is lower than the first voltage develops on the node from the second voltage supply.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Beau D. Barry of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4091, G11C11/408, G11C11/4097
CPC Code(s): G11C11/4091
Abstract: a microelectronic device includes a memory array structure and a control circuitry structure overlying and bonded to the memory array structure. the memory array structure includes memory cells, digit lines, and word lines. the control circuitry structure includes a control circuitry region, digit line contact sections, and word line contact sections. the control circuitry region includes sense amplifier sections including sense amplifiers, and sub-word line driver sections including sub-word line drivers. the digit line contact sections are horizontally adjacent to the sense amplifier sections in a first direction and include contact structures coupled to the sense amplifiers and the digit lines. the word line contact sections are horizontally adjacent to the sub-word line driver sections in a second direction orthogonal to the first direction and include additional contact structures coupled to the sub-word line drivers and the word lines. additional microelectronic devices, memory devices, and electronic systems are also described.
Inventor(s): Fatma Arzum Simsek-Ege of Boise ID (US) for micron technology, inc., Beau D. Barry of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4091, G11C5/06, G11C11/408, G11C11/4097
CPC Code(s): G11C11/4091
Abstract: a microelectronic device includes a memory array structure and a control circuitry structure vertically overlying and bonded to the memory array structure. the memory array structure includes array regions respectively including memory cells, digit lines, and word lines within horizontal areas thereof. the control circuitry structure includes control circuitry regions, sense amplifier (sa) sections including sa circuitry, and sub-word line driver (swd) sections including swd circuitry. the control circuitry regions horizontally overlap the array regions of the memory array structure. the sa sections respectively horizontally overlap each of two of the control circuitry regions horizontally neighboring one another in a first direction. the swd sections are respectively interposed between two other of the control circuitry regions horizontally neighboring one another in a second direction orthogonal to the first direction. additional microelectronic devices, memory devices, and electronic systems are also described.
Inventor(s): Wenlun Zhang of Chofu (JP) for micron technology, inc., Hiroki Fujisawa of Sagamihara (JP) for micron technology, inc., Shinichi Miyatake of Sagamihara (JP) for micron technology, inc., Yuan He of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C11/4091, G11C5/14, G11C11/4096
CPC Code(s): G11C11/4091
Abstract: sense amplifiers for memory devices may include threshold voltage compensation circuitry configured to compensate a threshold voltage offset of a portion of the sense amplifier. additionally, the sense amplifiers also perform pre-sensing of the portion of the sense amplifier. moreover, the sense amplifier is configured to perform main sensing and latching in a phase after pre-sensing the portion of the sense amplifier.
20240290379. MANAGING MEMORY BASED ON ACCESS DURATION_simplified_abstract_(micron technology, inc.)
Inventor(s): Riccardo Pazzocco of Verona (IT) for micron technology, inc., Angelo Visconti of Appiano Gentile (IT) for micron technology, inc.
IPC Code(s): G11C11/4096, G11C11/4076, G11C11/408, G11C11/4093
CPC Code(s): G11C11/4096
Abstract: methods, systems, and devices for managing memory based on access duration are described. a memory device may include a first set of memory cells resilient against access durations of a first duration and a second set of memory cells resilient against access durations of a shorter duration. a command for accessing the memory device may be received. the command may be associated with an access duration. whether to access, as part of executing the command, the first set of memory cells or the second set of memory cells may be determined based on the access duration. the first set of memory cells may be accessed, as part of executing the command, based on the access duration being greater than a threshold duration. or the second set of memory cells may be accessed based on the access duration being less than or equal to the threshold duration.
Inventor(s): James E. Davis of Meridian ID (US) for micron technology, inc., Shyam Surthi of Boise ID (US) for micron technology, inc., Martin W. Popp of Meridian ID (US) for micron technology, inc., KangYoul Lee of Sunnyvale CA (US) for micron technology, inc., Yui Shimizu of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/04, H01L23/528
CPC Code(s): G11C16/0483
Abstract: a microelectronic device comprises, a control circuitry structure comprising an active region including control logic circuitry at least partially within a semiconductive material; a bond pad on a backside of the control circuitry structure; a conductive contact vertically extending from the bond pad, through the semiconductive material, and to the control logic circuitry; and a dielectric-filled slit vertically extending into the semiconductive material and horizontally circumscribing the conductive contact, portions of the semiconductive material horizontally interposed between the conductive contact and the dielectric-filled slit. additional microelectronic devices, memory devices, microelectronic device packages, and electronic systems are also described.
Inventor(s): Gianpietro Carnevale of Bottanuco (IT) for micron technology, inc.
IPC Code(s): G11C16/04, H10B41/10, H10B41/27, H10B41/35, H10B43/10, H10B43/27, H10B43/35
CPC Code(s): G11C16/0483
Abstract: a method used in forming memory circuitry comprises forming a stack comprising vertically-alternating different-composition first tiers and second tiers. channel-material strings extend through the first and second tiers. the channel material of an upper portion of the channel-material strings is part of individual select-gate transistors in a finished-circuitry construction. a lower portion of the channel-material strings is part of memory-cell strings in the finished-circuitry construction. the upper portion of the channel-material strings individually comprise a cylinder comprising the channel material of the individual select-gate transistors. a mid-material is formed within an internal volume of the cylinder radially-inside of the channel material. the mid-material material comprises conductivity-increasing dopant therein. the conductivity-increasing dopant is out-diffused from the mid-material into the channel material of the cylinder and the individual select-gate transistors. the mid-material is insulative or semiconductive in the finished-circuitry construction. other embodiments, including structure independent of method, are disclosed.
Inventor(s): Sheyang Ning of San Jose CA (US) for micron technology, inc., Lawrence Celso Miranda of San Jose CA (US) for micron technology, inc., Zhengyi Zhang of San Jose CA (US) for micron technology, inc., Tomoko Ogura Iwasaki of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/10, G11C16/04, G11C16/08, G11C16/24, G11C16/26, G11C16/34
CPC Code(s): G11C16/10
Abstract: control logic in a memory device causes a programming pulse of a set of programming pulses to be applied to a wordline associated with a memory cell of a memory device, where the memory cell is to be programmed to a target voltage level representing a first programming level. at a first time, first data is caused to be stored in a cache, the first data indicating that a threshold voltage of a memory cell exceeds the target voltage level. at a second time, the cache is caused to be refreshed to store second data indicating that the threshold voltage of the memory cell is less than the target voltage level. in view of the second data, a level shifting operation associated with the memory cell is caused to be executed.
20240290391. COMPLEX PAGE ACCESS IN MEMORY DEVICES_simplified_abstract_(micron technology, inc.)
Inventor(s): Dmitri Yudanov of Sacramento CA (US) for micron technology, inc., Jeongsu Jeong of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C16/12
CPC Code(s): G11C16/12
Abstract: a system for providing complex page access in memory devices, such as hybrid-bonded memory is disclosed. the system receives a plurality of requests for data, such as from a host device. the system identifies a memory page of a memory device storing data bits corresponding to the requested data. the memory page may be spread across a plurality of sections of a memory bank of the memory device. each section of the memory bank being utilized for a portion of the memory page may be addressable by a separate row address. the system activates the memory page as a whole and enables the data to be accessed from different memory rows in different sections of the memory page of the memory device using the separate row addresses. the system accomplishes the foregoing instead of requiring access from only a single location of the memory bank at a time.
20240290392. DECK-BASED ERASE FUNCTION_simplified_abstract_(micron technology, inc.)
Inventor(s): Nikhil Birgade of Hyderabad (IN) for micron technology, inc., Uday Bhasker V. Vudugandla of Hyderabad (IN) for micron technology, inc.
IPC Code(s): G11C16/16, G11C16/10, G11C16/32
CPC Code(s): G11C16/16
Abstract: methods, systems, and devices for a deck-based erase function are described. a memory system may perform alternating erase operations and write operations on a virtual block configured with blocks constructed from half good blocks (hgbs). for example, the memory system may erase and subsequently write data to a first subset of hgbs associated with one or more memory dies of the memory system, before erasing and subsequently writing data to a second subset of hgbs associated with the one or more memory dies. in some cases, the memory system may determine the first subset of hgbs has been filled by the write operations, prior to erasing the second subset of hgbs. in other cases, the memory system may identify an idle time during writing to the first subset of hgbs, and begin erasing the second subset of hgbs during the idle time.
Inventor(s): Liang Yu of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc., Tal Sharifie of Lehavim (IL) for micron technology, inc.
IPC Code(s): G11C16/30, G06F12/02
CPC Code(s): G11C16/30
Abstract: methods, systems, and devices for power management associated with memory and a controller are described. a memory system performs a power management operation that accounts for power usage by any combination of application specific integrated circuits (asics) and memory arrays. the power management operation includes multiple logical unit numbers (luns) assigned to a single asic, which increases a quantity of bits for communicating a power usage. an asic included in a memory system may utilize twice as many bits for communicating power usage information when compared to a nand array. as part of the power management operation, an asic may transmit, to a controller, a first set of bits indicating a power usage of the asic, a first subset of the set of bits transmitted during a first instance of a token ring and a second subset of the set of bits transmitted during a second instance of the token ring.
Inventor(s): Christina Papagianni of San Jose CA (US) for micron technology, inc., Murong Lang of San Jose CA (US) for micron technology, inc., Zhenming Zhou of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/10
CPC Code(s): G11C16/3459
Abstract: a request to perform a program operation on a memory cell of a memory device is received. a number of program erase cycles (pecs) associated with the memory device is determined. a temperature of the memory device is determined. a gate voltage step adjustment value and a program verify level adjustment value is determined based on the temperature and the number of pecs. a default gate voltage step is adjusted based the gate voltage step adjustment value. a default program verify level is adjusted based the program verify level adjustment value.
20240290406. MEMORY DEVICE WEAR LEVELING_simplified_abstract_(micron technology, inc.)
Inventor(s): Rainer Frank BONITZ of Bruckmühl (DE) for micron technology, inc.
IPC Code(s): G11C16/34, G11C16/04, G11C16/16, G11C16/26
CPC Code(s): G11C16/349
Abstract: a controller of a memory device may determine that an endurance parameter associated with a wear leveling pool of a memory of the memory device satisfies a threshold. the wear leveling pool includes a plurality of memory blocks of the memory. the controller may divide, based on determining that the endurance parameter satisfies the threshold, the plurality of memory blocks of the wear leveling pool into a first wear leveling pool subset that includes a first subset of the plurality of memory blocks and a second wear leveling pool subset that includes a second subset of the plurality of memory blocks. a first subset of a plurality of data partitions is stored in the first subset of the plurality of memory blocks, and a second subset of the plurality of data partitions is stored in the second subset of the plurality of memory blocks.
Inventor(s): Matthew A. Prather of San Jose CA (US) for micron technology, inc.
IPC Code(s): G11C29/02, G11C17/16, G11C17/18
CPC Code(s): G11C29/027
Abstract: memory devices may be assigned enumeration values that uniquely identify the memory devices in a multi-memory device system. in some examples, the enumeration value is assigned by programming one or more fuses in the memory device. in some examples, a post-package repair operation may be used to program the fuses.
Inventor(s): Chun S. Yeung of San Jose CA (US) for micron technology, inc., Deping He of Boise ID (US) for micron technology, inc., Jonathan S. Parry of Boise ID (US) for micron technology, inc.
IPC Code(s): G11C29/42, G11C7/04, G11C29/12, G11C29/44
CPC Code(s): G11C29/42
Abstract: methods, systems, and devices for topology-based retirement in a memory system are described. in some examples, a memory system or memory device may be configured to evaluate error conditions relative to a physical or electrical organization of a memory array, which may support inferring the presence or absence of defects in one or more structures of a memory device. for example, based on various evaluations of detected errors, a memory system or a memory device may be able to infer a presence of a short-circuit, an open circuit, a dielectric breakdown, or other defects of a memory array that may be related to wear or degradation over time, and retire a portion of a memory array based on such an inference.
Inventor(s): Dongxiang Liao of Cupertino CA (US) for micron technology, inc., Tomer Tzvi Eliash of Sunnyvale CA (US) for micron technology, inc.
IPC Code(s): G11C29/44, G11C16/28
CPC Code(s): G11C29/44
Abstract: a boot-up read pattern data structure is maintained. each entry of the boot-up read pattern data structure comprises a boot-up read pattern associated with a respective power cycle event and a dummy boot-up read pattern flag. the dummy boot-up read pattern flag indicates that the boot-up read pattern has been consecutively used during boot-up. storing, in a new entry of the boot-up read pattern data structure, a current boot-up read pattern associated with a respective power cycle event for each power cycle event. the current boot-up read pattern with a previous boot-up read pattern associated with a latest entry of the boot-up pattern data structure is compared. a dummy boot-up read pattern flag of the new entry is updated responsive to the comparing the current boot-up read pattern and the previous boot-up read pattern.
Inventor(s): Matthew B. Leslie of Boise ID (US) for micron technology, inc., Timothy M. Hollis of Boise ID (US) for micron technology, inc., Roy E. Greeff of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L25/065, H01L25/00
CPC Code(s): H01L25/0652
Abstract: apparatuses and methods for coupling semiconductor devices are disclosed. terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. the conductive structures may be included in a redistribution layer (rdl) structure. the rdl structure may have a “u” shape in some embodiments of the disclosure. each end of the “u” shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the rdl structure. the conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). as a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the rdl structures, conductive bond pads, and conductors.
Inventor(s): Michael A. Smith of Boise ID (US) for micron technology, inc.
IPC Code(s): H01L27/092, H01L21/762, H01L23/00, H01L23/528, H10B80/00
CPC Code(s): H01L27/092
Abstract: a string driver device including a substrate; and a plurality of string driver array blocks that are disposed above the substrate, each of the plurality of string driver array blocks including a plurality of active regions that are parallelly aligned along a length direction, a plurality of shared gates that are disposed above the plurality of active regions and along a width direction, the width direction being perpendicular to the length direction, a through silicon isolation (tsi) region that surrounds the plurality of active regions on the substrate and that is disposed between neighboring active regions of the plurality of active regions, and a plurality of shallow trench isolation (sti) regions that are disposed adjacent to one or more channel regions of each of the plurality of active regions and below the plurality of shared gates respectively.
Inventor(s): Fa-Long Luo of San Jose CA (US) for micron technology, inc., Jaime Cummins of Bainbridge Island WA (US) for micron technology, inc.
IPC Code(s): H01Q1/22, G06F13/42, H04W76/16
CPC Code(s): H01Q1/2283
Abstract: examples described herein include an apparatus that includes a device having a first semiconductor chip and a second semiconductor chip. the first semiconductor chip has a configurable baseband processor that is configured to mix input data with a first set of weight values corresponding to a first wireless protocol to be utilized in a wireless, rf transmission to the second semiconductor chip when the input data is a first type of data and to mix the input data with a second set and to mix the input data with a second set of weight values corresponding to a second wireless protocol to be utilized in the wireless, rf transmission to the second semiconductor chip when the input data is a second type of data.
Inventor(s): Jinha Hwang of Boise ID (US) for micron technology, inc.
IPC Code(s): H03K19/0185, H03F3/45, H03K3/012, H03K3/356
CPC Code(s): H03K19/018528
Abstract: a semiconductor device includes a first sensing stage configured to sense a voltage differential of a data signal and a reference signal and output a first amplified voltage differential, wherein the first amplified voltage differential includes a first voltage at a first output node and a second voltage at a second output node. the semiconductor device further includes a second sensing stage configured to sense the first amplified voltage differential and output a second amplified voltage differential, where the second amplified voltage differential includes a third voltage at a third output node and a fourth voltage at a fourth output node. a first power gating circuit is coupled to the third output node and a second power gating circuit is coupled to the fourth output node.
Inventor(s): Christophe Vincent Antoine Laurent of Agrate Brianza (MB) (IT) for micron technology, inc.
IPC Code(s): H03M13/15, H03M13/00, H03M13/11
CPC Code(s): H03M13/1575
Abstract: in some aspects, the techniques described herein relate to a method including: receiving a standard error code correction (ecc) matrix, the standard ecc matrix including a portion for checking a payload and a portion for checking a parity of the payload; and extending the ecc matrix to form an extended matrix by adding a plurality of rows and a plurality of columns to form an upper matrix and a lower matrix, wherein the plurality of rows and columns include at least one all zero portion, at least one portion for checking a quantized knuth (qk) index, and a portion for checking a parity of the qk index.
Inventor(s): Fa-Long Luo of San Jose CA (US) for micron technology, inc., Jaime Cummins of Bainbridge Island WA (US) for micron technology, inc.
IPC Code(s): H04B1/10, H04B17/345, H04B17/391
CPC Code(s): H04B1/1036
Abstract: a wireless device includes a wireless receiver configured to receive a respective plurality of receive signals from a respective receiving antenna of a plurality of receiving antennas and an interference mitigation circuit coupled to the respective receiving antenna and including a neural network. the interference mitigation circuit is configured to receive an interference mitigation mode signal indicating two or more interference types of a plurality of interference types to mitigate. in response to the interference mitigation mode signal, the interference mitigation circuit is configured to adjust weights applied by the neural network for adjusted signals to cause the neural network to mitigate the two or more interference types of the plurality of interference types while receiving the plurality of receive signals.
Inventor(s): Prasad Nagavenkata Nune of Hyderabad (IN) for micron technology, inc., Christopher Glancey of Boise ID (US) for micron technology, inc., Yeow Chon Ong of Singapore (SG) for micron technology, inc., Hong Wan Ng of Singapore (SG) for micron technology, inc.
IPC Code(s): H05K1/02
CPC Code(s): H05K1/0271
Abstract: a microelectronic device package assembly includes a package board and a stiffener device attached to the package board. the package board has a first side and a second side. the stiffener device includes an upper stiffener, a lower stiffener, and one or more damper device. the upper stiffener is above the first side of the package board and has a die side and a package side. the lower stiffener is interposed between the upper stiffener and the package board and has a damper side and a board side. the lower stiffener includes through-package anchors extending from the board side and through the package board. the one or more damper devices are interposed between and are in contact with each of the upper stiffener and the lower stiffener. microelectronic devices and electronic systems are also described.
20240292603. DAMASCENE DIGIT LINES_simplified_abstract_(micron technology, inc.)
Inventor(s): Russell A. Benson of Boise ID (US) for micron technology, inc., Terrence B. McDaniel of Boise ID (US) for micron technology, inc., Vinay Nair of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B12/00, H01L21/762
CPC Code(s): H10B12/482
Abstract: systems, methods and apparatus are provided for damascene digit lines. for instance, a damascene digit line can be formed by forming a plurality of dummy digit lines on a semiconductor substrate that are separated by a first set of vertical trenches, depositing a sacrificial insulating material in the first set of vertical trenches, forming, and depositing an insulating fill material in, a second set of vertical trenches, forming, and depositing a nitride material in, nitride material deposition spaces; removing at least a portion of the semiconductor substrate to form plurality of cell contact deposition spaces, forming cell contacts in the cell contact deposition spaces, removing the dummy digit lines to form a plurality of vertical openings, removing nitride material to form expanded vertical opening, depositing a digit line insulating material in the expanded vertical openings to form digit line deposition spaces, and forming digit lines.
20240292607. SELF-ALIGNED LINE CONTACTS_simplified_abstract_(micron technology, inc.)
Inventor(s): Jun Ho Lee of Higashihiroshima City (JP) for micron technology, inc., Byung Yoon Kim of Boise ID (US) for micron technology, inc., Sangmin Hwang of San Jose CA (US) for micron technology, inc.
IPC Code(s): H10B12/00
CPC Code(s): H10B12/488
Abstract: a variety of applications can include an apparatus having a device including line contacts to closely-spaced conductive signal lines structured such that a sufficient margin for shorts between a signal line and a line contact to a directly adjacent signal line is maintained even with a misalignment of the line contact. in an embodiment, formation of a memory device can include forming a line contact on and contacting an access line for an array of memory cells, using a two stage removal procedure of different removal processes. the two stage removal procedure can include removing a portion of processing layers above an insulating protective layer positioned on the access line and selectively removing the insulating protective layer, exposing a portion of the access line, without removing material of the access line. the line contact can be formed on and contacting the top exposed portion of the access line.
Inventor(s): Shuangqiang Luo of Boise ID (US) for micron technology, inc., Indra V. Chary of Boise ID (US) for micron technology, inc., Justin B. Dorhout of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B43/27, H01L21/768, H01L23/00, H01L23/532, H01L23/535, H10B41/27
CPC Code(s): H10B43/27
Abstract: a microelectronic device may include a stack structure comprising a vertically alternating sequence of insulative structures and conductive structures, the stack structure divided into block portions. the microelectronic device may additionally include slit structures horizontally interposed between the block portions of the stack structure. each of the slit structures may include a dielectric liner covering side surfaces of the stack structure and an upper surface of an additional structure underlying the stack structure, and a plug structure comprising at least one metal surrounded by the dielectric liner.
Inventor(s): Riccardo Pazzocco of Verona (IT) for micron technology, inc., Marcello Mariani of Milano (IT) for micron technology, inc., Giorgio Servalli of Fara Gera d'Adda (IT) for micron technology, inc.
IPC Code(s): H10B53/30, H01L21/28, H01L29/51, H01L29/66, H01L29/78, H10B51/10, H10B51/30, H10B53/10
CPC Code(s): H10B53/30
Abstract: a variety of applications can include apparatus having a memory device with ferroelectric capacitors as storage structures in memory cells. the ferroelectric capacitors can be arranged vertically from a region of access transistors of the memory cells with the bottom electrodes of the ferroelectric capacitors arranged above and coupled to the access transistors. the bottom electrodes can be separated from the top electrodes of the ferroelectric capacitors by ferroelectric material. the bottom electrodes of ferroelectric capacitors of adjacent memory cells can be separated by a low-k dielectric material.
Inventor(s): Hernan A. Castro of Shingle Springs CA (US) for micron technology, inc., Stephen H. Tang of Fremont CA (US) for micron technology, inc., Stephen W. Russell of Boise ID (US) for micron technology, inc.
IPC Code(s): H10B63/00, H10B53/20, H10N70/20
CPC Code(s): H10B63/845
Abstract: methods and apparatuses for a cross-point memory array and related fabrication techniques are described. the fabrication techniques described herein may facilitate concurrently building two or more decks of memory cells disposed in a cross-point architecture. each deck of memory cells may include a plurality of first access lines (e.g., word lines), a plurality of second access lines (e.g., bit lines), and a memory component at each topological intersection of a first access line and a second access line. the fabrication technique may use a pattern of vias formed at a top layer of a composite stack, which may facilitate building a 3d memory array within the composite stack while using a reduced number of processing steps. the fabrication techniques may also be suitable for forming a socket region where the 3d memory array may be coupled with other components of a memory device.
20240292766. CHALCOGENIDE MEMORY DEVICE COMPOSITIONS_simplified_abstract_(micron technology, inc.)
Inventor(s): Dale W. Collins of Boise ID (US) for micron technology, inc., Paolo Fantini of Vimercate (MB) (IT) for micron technology, inc., Lorenzo Fratin of Buccinasco (MI) (IT) for micron technology, inc., Enrico Varesi of Milano (MI) (IT) for micron technology, inc.
IPC Code(s): H10N70/00, C01B17/02, C01B19/04, H10B63/00, H10B63/10
CPC Code(s): H10N70/8822
Abstract: methods, systems, and devices for chalcogenide memory device compositions are described. a memory cell may use a chalcogenide material having a composition as described herein as a storage materials, a selector materials, or as a self-selecting storage material. a chalcogenide material as described herein may include a sulfurous component, which may be completely sulfur (s) or may be a combination of sulfur and one or more other elements, such as selenium (se). in addition to the sulfurous component, the chalcogenide material may further include one or more other elements, such as germanium (ge), at least one group-iii element, or arsenic (as).
Micron Technology, Inc. patent applications on August 29th, 2024
- Micron Technology, Inc.
- C23C16/455
- CPC C23C16/45553
- Micron technology, inc.
- G01R31/01
- G01R27/26
- CPC G01R31/016
- G01R31/3185
- G01R31/28
- G01R31/317
- CPC G01R31/318597
- G11C16/30
- CPC G06F1/3225
- G06F1/3225
- G06F13/16
- G06F13/40
- G06F3/06
- CPC G06F3/0611
- CPC G06F3/0619
- CPC G06F3/0632
- CPC G06F3/064
- CPC G06F3/0656
- CPC G06F3/0659
- G06F9/455
- G06F8/61
- CPC G06F9/45558
- G06F11/10
- CPC G06F11/1068
- G06F11/07
- G06F11/14
- G11C11/56
- G11C16/26
- G11C29/02
- G11C29/44
- G11C29/52
- CPC G06F11/142
- CPC G06F11/1469
- G06F11/263
- G06F11/22
- CPC G06F11/263
- G06F12/02
- CPC G06F12/0223
- G06F9/54
- G06F12/0815
- CPC G06F12/0246
- G06F12/06
- G06F13/42
- G06F12/0882
- G06F12/1009
- CPC G06F12/1009
- G06F12/14
- CPC G06F12/1491
- G06N3/049
- G06N3/065
- G06N3/084
- G06N5/046
- G11C13/00
- H03M1/12
- CPC G06N3/049
- G06N3/098
- G06N3/04
- CPC G06N3/098
- G11C7/22
- G11C7/10
- CPC G11C7/222
- G11C11/408
- G11C5/14
- G11C11/22
- G11C11/4094
- CPC G11C11/4085
- G11C11/4091
- G11C11/4097
- CPC G11C11/4091
- G11C5/06
- G11C11/4096
- G11C11/4076
- G11C11/4093
- CPC G11C11/4096
- G11C16/04
- H01L23/528
- CPC G11C16/0483
- H10B41/10
- H10B41/27
- H10B41/35
- H10B43/10
- H10B43/27
- H10B43/35
- G11C16/10
- G11C16/08
- G11C16/24
- G11C16/34
- CPC G11C16/10
- G11C16/12
- CPC G11C16/12
- G11C16/16
- G11C16/32
- CPC G11C16/16
- CPC G11C16/30
- CPC G11C16/3459
- CPC G11C16/349
- G11C17/16
- G11C17/18
- CPC G11C29/027
- G11C29/42
- G11C7/04
- G11C29/12
- CPC G11C29/42
- G11C16/28
- CPC G11C29/44
- H01L25/065
- H01L25/00
- CPC H01L25/0652
- H01L27/092
- H01L21/762
- H01L23/00
- H10B80/00
- CPC H01L27/092
- H01Q1/22
- H04W76/16
- CPC H01Q1/2283
- H03K19/0185
- H03F3/45
- H03K3/012
- H03K3/356
- CPC H03K19/018528
- H03M13/15
- H03M13/00
- H03M13/11
- CPC H03M13/1575
- H04B1/10
- H04B17/345
- H04B17/391
- CPC H04B1/1036
- H05K1/02
- CPC H05K1/0271
- H10B12/00
- CPC H10B12/482
- CPC H10B12/488
- H01L21/768
- H01L23/532
- H01L23/535
- CPC H10B43/27
- H10B53/30
- H01L21/28
- H01L29/51
- H01L29/66
- H01L29/78
- H10B51/10
- H10B51/30
- H10B53/10
- CPC H10B53/30
- H10B63/00
- H10B53/20
- H10N70/20
- CPC H10B63/845
- H10N70/00
- C01B17/02
- C01B19/04
- H10B63/10
- CPC H10N70/8822
