International Business Machines Corporation patent applications on October 17th, 2024
Patent Applications by International Business Machines Corporation on October 17th, 2024
International Business Machines Corporation: 30 patent applications
International Business Machines Corporation has applied for patents in the areas of H10N50/85 (4), H10B61/00 (4), H10N50/01 (4), H01F10/32 (3), G11C11/16 (2) H10N50/80 (2), G05B19/042 (1), G06V20/56 (1), H10N50/85 (1), H05K7/20272 (1)
With keywords such as: computer, data, dielectric, user, environment, based, power, cooling, array, and input in patent application abstracts.
Patent Applications by International Business Machines Corporation
Inventor(s): Sarbajit K. Rakshit of Kolkata (IN) for international business machines corporation, Jagabondhu Hazra of Bangalore (IN) for international business machines corporation, Manikandan Padmanaban of Chennai (IN) for international business machines corporation, Marc Henri Coq of Hopewell Junction NY (US) for international business machines corporation
IPC Code(s): G05B19/042
CPC Code(s): G05B19/042
Abstract: management of thermal energy from a computer data center to generate an electrical power output using a thermoelectric generator can include a computer managing thermal output of heat at a location at a computer data center, where the location corresponds to a heat generating computer component. heat flow is managed from the thermal output using a heating thermal conduit thermally communicating with a heat source of a thermoelectric generator. an electrical output generated by the thermoelectric generator is controlled using the management of the heat flow from the thermal output.
Inventor(s): Xiang Yu Xue of Beijing (CN) for international business machines corporation, Bo Chen Zhu of Xi'an (CN) for international business machines corporation, HUI WANG of Beijing (CN) for international business machines corporation, Mai Zeng of Beijing (CN) for international business machines corporation, Xiao Chen Huang of Beijing (CN) for international business machines corporation, Peng Hui Jiang of Beijing (CN) for international business machines corporation, Wei Li of Beijing (CN) for international business machines corporation, Yu Mei Dai of Beijing (CN) for international business machines corporation
IPC Code(s): G06F9/4401, G06F9/455
CPC Code(s): G06F9/442
Abstract: a method, computer system, and a computer program product are provided for managing an accelerated shutdown of a networked system having a having a plurality of nodes. the system to be shutdown is analyzed and a priority order is determined for the nodes. an interval period is also determined between each node according to the priority order. a leaf node set is constructed according to different shutdown types required for each node and a dependency tree is constructed by analyzing the leaf node sets. each node is then shutdown according to the tree and the interval period determined. the dependency tree and the interval period is iteratively modified during the node shutdown until all nodes and ultimately the system shutdown has been completed.
Inventor(s): Robert WOOLF of Raleigh NC (US) for international business machines corporation, Gregory A. JOHNSON of Wilmington NC (US) for international business machines corporation, Neil Delima of Scarborough (CA) for international business machines corporation, Girish PADMANABHAN of Pune (IN) for international business machines corporation
IPC Code(s): G06F9/455
CPC Code(s): G06F9/45558
Abstract: automatic generation of service instance managers includes automatically generating, from a first representation of a service instance manager for an environment, a second representation of the service instance manager. the first representation and second representation are programmed in different technologies. the automatically generating includes obtaining a universal form into which the first representation was transformed via a transformation, and further includes generating the second representation using the universal form and variable information, recovered from the first representation, lost by the transformation of the first representation into the universal form.
Inventor(s): Lior Aronovich of Thornhill (CA) for international business machines corporation
IPC Code(s): G06F9/50
CPC Code(s): G06F9/5077
Abstract: a computer-implemented method, a computer program product, and a computer system for global vertical auto-scaling for processing units. a computer periodically learns one or more functions, based on resource consumption metrics samples of processing units. a computer uses the one or more functions to obtain a predicted maximal resource consumption value per resource and a predicted minimal resource consumption value per resource for a processing unit. a computer determines a global priority of the processing unit. a computer calculate a prioritized predicted consumption value per resource for the processing unit, based on the global priority, the predicted maximal resource consumption value, and the predicted minimal resource consumption value. a computer uses the prioritized predicted consumption value for vertical auto-scaling of the processing unit by a processing unit management system.
Inventor(s): Oleksandr Osadchyy of Concord CA (US) for international business machines corporation, Christopher Thomas Vogan of Cedar Park TX (US) for international business machines corporation
IPC Code(s): G06F9/54
CPC Code(s): G06F9/541
Abstract: performing container layer translation across different types of processor architectures is provided. dynamic mapping of respective source image layers of an original source container image built for a first type of processor architecture to corresponding target image layers for a second type of processor architecture that is different from the first type of processor architecture is performed. computational resource ratios needed to run dynamically mapped image layers of a target container image using the second type of processor architecture is determined based, at least in part, on a technical stack type of an application associated with the respective source image layers of the original source container image. the target container image having the dynamically mapped image layers along with the computational resource ratios is served to a target host computer node that includes the second type of processor architecture via a network.
Inventor(s): Lior Horesh of North Salem NY (US) for international business machines corporation, Cristina Cornelio of Kilchberg (CH) for international business machines corporation, Sanjeeb Dash of Croton on Hudson NY (US) for international business machines corporation, Joao P. Goncalves of Wappingers Falls NY (US) for international business machines corporation, Kenneth Lee Clarkson of Madison NJ (US) for international business machines corporation, Nimrod Megiddo of Palo Alto CA (US) for international business machines corporation, Bachir El Khadir of White plains NY (US) for international business machines corporation, Vernon Ralph Austel of Cortlandt Manor NY (US) for international business machines corporation
IPC Code(s): G06F17/11
CPC Code(s): G06F17/11
Abstract: a method for obtaining a refined model given a mis-specified symbolic model. the method includes receiving a mis-specified symbolic model and data pertaining to a process or phenomenon corresponding to the mis-specified symbolic model; receiving one or more constraints; generating a plurality of partial expression trees based on the mis-specified symbolic model; solving an optimization problem for each of the partial expression trees; and determining a refined symbolic model of the mis-specified symbolic model based on results of the optimization problem for each partial expression tree.
Inventor(s): Sunyanan Choochotkaew of Koto (JP) for international business machines corporation, Tatsuhiro Chiba of Bunkyo-ku (JP) for international business machines corporation, Marcelo Carneiro Do Amaral of Tokyo (JP) for international business machines corporation, Eun Kyung Lee of Bedford Corners NY (US) for international business machines corporation
IPC Code(s): G06F30/27
CPC Code(s): G06F30/27
Abstract: described are techniques for modeling power in the multi-tenant private cloud environment. an absolute power model is trained to estimate the absolute power in the multi-tenant private cloud environment. the absolute power model is composed of both independent and dependent inferences. furthermore, a dynamic power model is trained to estimate the dynamic power in the multi-tenant private cloud environment based on the deconstructed independent inferences. the dynamic power model is composed of only the deconstructed independent inferences. the absolute power model and the dynamic power model are then combined into a combined model to model the power in the multi-tenant private cloud environment after validating the dynamic power model. the combined model may then be utilized to estimate the power used in the multi-tenant private cloud environment if the error metrics of the combined model indicate that a measured error of the combined model is less than a threshold value.
Inventor(s): Odellia Boni of Giva'at Ela (IL) for international business machines corporation, Michal Shmueli-Scheuer of Tel-Aviv (IL) for international business machines corporation, Kshitij Fadnis of Astoria NY (US) for international business machines corporation, Pankaj Dhoolia of Ghaziabad (IN) for international business machines corporation
IPC Code(s): G06F40/166, G06F16/23, G06F16/958, G06F40/14, G06F40/197, G06F40/30
CPC Code(s): G06F40/166
Abstract: systems and techniques that facilitate context-aware edit management of webpage-based applications are provided. in various embodiments, a system can detect an edit made to a webpage. in various aspects, the system can determine whether a webpage-based application associated with the webpage is consistent with the edit, based on a registry that respectively maps outputs of the webpage-based application to source texts and corresponding semantic contexts of a pre-edit version of the webpage.
Inventor(s): Giovanni Cherubini of Rueschlikon (CH) for international business machines corporation, Marcel A. Kossel of Reichenburg (CH) for international business machines corporation
IPC Code(s): G06N3/049, G06N3/08
CPC Code(s): G06N3/049
Abstract: a method of executing a time-encoded spiking neural network (tsnn) that includes configuring an electronic circuit connecting pairs of neurons of the tsnn, wherein each pair of the pairs of neurons connects a sender neuron to a receiver neuron through parallel channels, and operating the electronic circuit at an actual clock rate corresponding to actual time steps, for the electronic circuit to perform signaling over said each pair at each time step of the actual time steps by sending signals in parallel across the parallel channels. sent signals encode subcycle timing information about a timing of spikes relative to subcycle time steps, a unit duration that corresponds to a duration of said each time step divided by a latency reduction factor (lrf), for the operated electronic circuit to emulate an execution of the tsnn at an effective clock rate corresponding to the actual clock rate multiplied by the lrf.
Inventor(s): Shirley M. Han of New York NY (US) for international business machines corporation, Rama Kalyani T. Akkiraju of Cupertino CA (US) for international business machines corporation, Xiaotong Liu of San Jose CA (US) for international business machines corporation, Salil Ahuja of Washington DC (US) for international business machines corporation, Isabell Sippli of Metzingen (DE) for international business machines corporation
IPC Code(s): G06N3/08, G06Q30/04
CPC Code(s): G06N3/08
Abstract: an embodiment includes detecting incident data and resolution data in monitored data collected while monitoring an information technology (it) environment. the embodiment correlates the incident data with the resolution data according to a detected change in health metrics data from the monitored data. the embodiment stores the correlated incident data and resolution data as a training dataset stored in a database and then trains a machine learning model using the training dataset. the embodiment deploys the trained machine learning model such that the trained machine learning model provides resolution recommendation in response to receiving new incident data.
Inventor(s): Joseph Shtok of Binyamina (IL) for international business machines corporation, LEONID KARLINSKY of Acton MA (US) for international business machines corporation, Simon Magnus Tannert of Stuttgart (DE) for international business machines corporation, Jasmina Bogojeska of Adliswil (CH) for international business machines corporation, Marcelo Gabriel Feighelstein of Zychron Yaakov (IL) for international business machines corporation
IPC Code(s): G06N5/022, G06F16/901
CPC Code(s): G06N5/022
Abstract: aspects of the disclosure include methods, systems, and computer program products for generating semantically meaningful question-answer pairs for graph-like charts, such as flowcharts. in one example, a method of implementing a question answering (qa) system may comprise generating a synthetic dataset of graph-like chart images. the generating may comprise rendering a plurality of graph-like chart images from a plurality of associated graph data, generating a plurality of question-answer pairs for each of the graph-like chart images, and calculating a plurality of ground truth annotations for each of the plurality of question-answer pairs and associated graph-like chart images from the plurality of associated graph data. the method of implementing the qa system may further comprise training a vision-language architecture on the synthetic dataset to answer questions about the graph-like chart images.
Inventor(s): Naoki Kanazawa of Yokohama (JP) for international business machines corporation, Daniel Josef Egger of Zurich (CH) for international business machines corporation, Kento Ueda of Tokyo (JP) for international business machines corporation
IPC Code(s): G06N10/40
CPC Code(s): G06N10/40
Abstract: a quantum noise mitigation system can comprise a memory that stores, and a processor that executes, computer executable components comprising a pulse calibration component that, for controlling execution of a quantum gate of a quantum circuit, calibrates an echo extender tone parameter for a set of echo extender tones of an echo pulse sequence, wherein the pulse calibration component inserts the set of echo extender tones into the echo pulse sequence of an initial pulse sequence resulting in generation of a modified pulse sequence for use in controlling the execution of the quantum gate, and a parameterizing component that parameterizes the set of echo extender tones using a scalable stretch factor for stretching respective durations of the set of echo extender tones.
Inventor(s): Ana Paula APPEL of São Paulo (BR) for international business machines corporation, Paulo RODRIGO CAVALIN of Rio de Janeiro (BR) for international business machines corporation, Graziella Martins CAPUTO of Katy TX (US) for international business machines corporation, Paula Fernanda PEREIRA of São Paulo (BR) for international business machines corporation
IPC Code(s): G06N20/20
CPC Code(s): G06N20/20
Abstract: a method, system, and computer program product are configured to: receive an input machine learning model being developed for deployment in a production environment; create a feature vector based on metadata of the input machine learning model and a data source used by the input machine learning model; determine a risk tier of the input machine learning model by classifying the input machine learning model into one of plural predefined tiers using the feature vector with a model-tiering machine learning model; and provide validation information to an evaluator wherein the validation information is based on the risk tier and is used to validate the input machine learning model in accordance with the risk tier.
Inventor(s): Zachary A. Silverstein of Georgetown TX (US) for international business machines corporation, Melanie Dauber of Oceanside NY (US) for international business machines corporation, Jacob Ryan Jepperson of St. Paul MN (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation, Spencer Thomas Reynolds of Austin TX (US) for international business machines corporation
IPC Code(s): G06T7/00, G06T5/00
CPC Code(s): G06T7/0002
Abstract: an approach for preventing anomalous appearance characteristics of a user during a video conference. the approach receives a user's video feed from a video conference comprising the user's video feed. the approach analyzes the user's video feed based on a comparison with a reference appearance model associated with the user. the approach detects, based on the analysis, anomalous appearance characteristics associated with the user. the approach notifies the user of the anomalous appearance.
Inventor(s): Ghazi Sarwat Syed of Kilchberg (CH) for international business machines corporation
IPC Code(s): G06T7/13, G06F17/16, G11C13/00
CPC Code(s): G06T7/13
Abstract: a method for a computational memory implementing a shape detection transformation using an integrated memristive computing crossbar array is disclosed. the method comprises using a first crossbar array tile of at least three crossbar tiles of a memristive computing crossbar array for a parametric space transformation of the shape detection transformation, wherein data of an image in a vectorized form is used as input for the first crossbar array, using an output of the first crossbar array tile as input for a second crossbar array tile for an accumulation operation of the shape detection transformation, and using an output of the second crossbar array tile as input for a third crossbar array tile for a shape tracing operation of the transformation, such that an output of the third crossbar array determines parameter values of a detected shape.
Inventor(s): ZACHARY A. SILVERSTEIN of AUSTIN TX (US) for international business machines corporation, JACOB RYAN JEPPERSON of ROCHESTER MN (US) for international business machines corporation, MELANIE DAUBER of NEW YORK NY (US) for international business machines corporation, JEREMY R. FOX of AUSTIN TX (US) for international business machines corporation, LOGAN BAILEY of SANDY SPRINGS GA (US) for international business machines corporation
IPC Code(s): G06V20/56, A47L9/00, A47L9/28, G05D1/00, G06V10/70, G06V20/17
CPC Code(s): G06V20/56
Abstract: a hazard identification system includes: a computer device comprising a hazard identification application; and a mobile robotic device for self-propelled movement within a designated environment and with an interface for communicating with the hazard identification application, the mobile robotic device further comprising a camera for imaging the designated environment. the hazard identification application is to receive imaging of the designated environment from the camera of the mobile robotic device and to identify hazards in the designated environment from the imaging.
Inventor(s): Wei Jun Zheng of Shanghai (CN) for international business machines corporation, Xiao Xia Mao of Shanghai (CN) for international business machines corporation, Yuan Jin of Shanghai (CN) for international business machines corporation, Qing Lu of Shanghai (CN) for international business machines corporation, Xiao Feng Ji of Shanghai (CN) for international business machines corporation, Steven Lee Fisher-Stawinski of Buffalo Grove IL (US) for international business machines corporation
IPC Code(s): G10L15/22, G10L15/02
CPC Code(s): G10L15/22
Abstract: techniques are described with respect to a system, method, and computer product for voice-based augmented reality locomotion. an associated method includes receiving a first linguistic input; and determining a label and a duration associated with the linguistic input based on an analysis of the first linguistic input. the method further including converting the label into a heading and the duration into a magnitude in a virtual environment; and merging the heading and magnitude in a vector in the virtual environment.
Inventor(s): Sagarika Mukesh of ALBANY NY (US) for international business machines corporation, Shravana Kumar Katakam of Lehi UT (US) for international business machines corporation, Tao Li of Slingerlands NY (US) for international business machines corporation, Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation
IPC Code(s): H01L23/48, H01L21/8234, H01L27/088, H01L29/06, H01L29/423, H01L29/66, H01L29/775, H01L29/786
CPC Code(s): H01L23/481
Abstract: embodiments of present invention provide a semiconductor structure. the structure includes an array of transistors on a semiconductor substrate, the array of transistors including a first transistor and a second transistor, the second transistor being next to the first transistor; and a metal connection between the first transistor and the second transistor, wherein the metal connection connects a first metal contact at a frontside of the array of transistors to a second metal contact at a backside of the array of transistors. a method of forming the same is also provided.
Inventor(s): SHIDONG LI of Hopewell Junction NY (US) for international business machines corporation, Kenneth Charles Marston of Poughquag NY (US) for international business machines corporation, Kalind BARAYA of West Lafayette IN (US) for international business machines corporation
IPC Code(s): H01L23/00, H01L23/373, H01L23/473
CPC Code(s): H01L24/32
Abstract: semiconductor structures are provided with five different cooling elements directly bonded to a semiconductor chip. the cooling element is directly bonded to the backside of a thinned semiconductor substrate or to the front side back-end-of-line (beol) interconnect wiring of the semiconductor chip. the cooling element replaces a carrier wafer on semiconductor chips with backside beol interconnect wiring. each of the five cooling elements provide better thermal conductivity for the semiconductor structure when directly bonded to the front side beol interconnect wiring than the carrier wafer typically bonded to a semiconductor chip with backside beol interconnect wiring. the cooling element is one of a copper cooling element with water-filled microchannels, or a copper plate, a silicon cooling element with water-filled microchannels, a silicon carbide plate, or a glass plate with copper-filled vias. the cooling element is directly bonded to the semiconductor chip by a hybrid bond.
Inventor(s): Ruilong Xie of Niskayuna NY (US) for international business machines corporation, Chanro Park of Clifton Park NY (US) for international business machines corporation, Min Gyu Sung of Latham NY (US) for international business machines corporation, Juntao Li of Cohoes NY (US) for international business machines corporation, Julien Frougier of Albany NY (US) for international business machines corporation
IPC Code(s): H01L27/088, H01L21/8234
CPC Code(s): H01L27/088
Abstract: embodiments of present invention provide a method of forming a semiconductor structure. the method includes forming a gate cut trench in a first region between a first and a second metal gate and in a second region between a first and a second source/drain region of a first and a second transistor respectively; depositing a dielectric liner in the trench lining sidewalls and a bottom of the trench; depositing a dielectric filler inside the trench above the dielectric liner, the dielectric liner thereby surrounding a bottom and sidewalls of the dielectric filler; depositing a dielectric cap covering the dielectric liner in the first region; etching the dielectric liner in the second region to create an opening exposing the source/drain region of the first transistor; and depositing a conductive material in the opening to form a source/drain contact of the first transistor. a structure formed thereby is also provided.
Inventor(s): Bodhisatwa Sadhu of Peekskill NY (US) for international business machines corporation, Herschel Akiba Ainspan of New Hempstead NY (US) for international business machines corporation, Zheng Xu of Wappingers Falls NY (US) for international business machines corporation, Armagan Dascurcu of New York NY (US) for international business machines corporation, Gary Kurtzman of Lago Vista TX (US) for international business machines corporation
IPC Code(s): H03L7/18, H03B5/12
CPC Code(s): H03L7/18
Abstract: a voltage-controlled oscillator (vco) includes a cross-coupled transconductance cell. a transformer comprising a primary coil and at least one secondary coil, wherein the primary coil is connected to the cross-coupled transconductance cell. a primary coil varactor is connected to the cross-coupled transconductance cell in parallel to the primary coil. a variable inductive tuning component connected to the at least one secondary coil. a mode switch connected to the at least one secondary coil and configured to select a frequency mode of operation of the vco by engaging or disengaging the variable inductive tuning component from operation with the primary coil varactor to generate oscillation at a center frequency of the vco.
Inventor(s): Dong Chen of Beijing (CN) for international business machines corporation, Yuan Jie Zhang of Ningbo (CN) for international business machines corporation, Ming Lei Zhang of Beijing (CN) for international business machines corporation, Yin Xi Guo of Beijing (CN) for international business machines corporation, Ting Ting Zhan of Beijing (CN) for international business machines corporation
IPC Code(s): H04L12/18
CPC Code(s): H04L12/1831
Abstract: a method, computer system, and a computer program product are provided for a restoring missing content to a user that was absent during a portion of a live event. the process will identify the absence period and that is being participated by a user and obtains extracted information relating to the user that was previously gathered from a variety of sources including past user interactions and a user profile. this information is further analyzed and prioritized according to user interest priority determined by the extracted information. this information is categorized into a first set of domains. information provided during the absence of the user will also be captured and categorized into a second set of domain categories. an intersection between the first and second set of domain categories will be found and prioritized by user interest. this will be presented to the user upon user's return.
Inventor(s): Mauro Marzorati of Lutz FL (US) for international business machines corporation, Paul Llamas Virgen of Guadalajara (MX) for international business machines corporation, Pedro Mauricio Manjarrez Gutierrez of Guadalajara (MX) for international business machines corporation, Karla Paulina Calderon Vaca of Zapopan (MX) for international business machines corporation
IPC Code(s): H04L9/40, G06F21/53
CPC Code(s): H04L63/1416
Abstract: according to one embodiment, a method, computer system, and computer program product for mitigating cyberattacks is provided. the present invention may include responding to a verification of a detected attack on a system, by detecting one or more modifications to one or more software components made by malicious network traffic; identifying the malicious network traffic; determining one or more compromised software components based on the detected one or more modifications and the identified malicious network traffic; performing digital twin simulation to evaluate one or more risks associated with the one or more compromised software components in order to identify the one or more software components to encapsulate; creating an encapsulated environment; provisioning the one or more software components to encapsulate to the encapsulated environment; and redirecting the malicious network traffic to the encapsulated environment.
Inventor(s): Aaron K. Baughman of Cary NC (US) for international business machines corporation, Eduardo Morales of Key Biscayne FL (US) for international business machines corporation, Jeremy R. Fox of Georgetown TX (US) for international business machines corporation
IPC Code(s): H04W64/00, H04B17/318, H04L41/16
CPC Code(s): H04W64/00
Abstract: a computer-implemented process using a queue management system includes the following operations. a user and a plurality of configurable nodes are identified in a scope of the queue management system. a proximity between the user and a particular one of the plurality of configurable nodes is dynamically determined in real-time. using a machine learning engine and based upon the proximity and historical data associated with the scope of the queue management system, a probability measure that the user will engage with the particular one of the plurality of configurable nodes is determined. based upon the probability measure exceeding a threshold, the user is added to a queue managed by the queue management system. based upon the user being added to the queue, a state of the one of the plurality of plurality of configuration nodes is altered by the queue management system.
Inventor(s): Phillip V. MANN of Rochester MN (US) for international business machines corporation, Christopher M. MARROQUIN of Rochester MN (US) for international business machines corporation, Ray Clement LANING of Paynesville MN (US) for international business machines corporation, Milnes P. DAVID of New Paltz NY (US) for international business machines corporation, Nathan Lee DUNFEE of Rochester MN (US) for international business machines corporation
IPC Code(s): H05K7/20
CPC Code(s): H05K7/20272
Abstract: embodiments of the disclosure provide cooling systems and cooling methods for isolating temperature fluctuation in an electronics enclosure. embodiments of the disclosure provide effective cooling of high power temperature fluctuating components and a stable reference temperature for temperature sensitive components included in a single electronics enclosure. a disclosed multiple path cooling system includes a first path for cooling power variable components and a second path to maintain stable temperature cooling for temperature sensitive components.
Inventor(s): Daniel Worledge of San Jose CA (US) for international business machines corporation, Guohan Hu of Yorktown Heights NY (US) for international business machines corporation
IPC Code(s): H10N50/80, G11C11/16, H01F10/32, H01F41/34, H10B61/00, H10N50/01, H10N50/85
CPC Code(s): H10N50/80
Abstract: a magnetoresistive random access memory (mram) including spin-transfer torque (stt) mram is provided that has enhanced data retention. the enhanced data retention is provided by constructing a mtj pillar having a temperature-independent delta, where delta is delta=eb/kt, wherein eb is the activation energy, k is the boltzmann's constant, and t is the absolute temperature. notably, the present application provides a way for eb to actually increase with temperature, which can cancel the effect of the term kt, resulting in a temperature independent delta.
Inventor(s): Takashi Ando of Eastchester NY (US) for international business machines corporation, Reinaldo Vega of Mahopac NY (US) for international business machines corporation, Nicholas Anthony Lanzillo of Wynantskill NY (US) for international business machines corporation, David Wolpert of Poughkeepsie NY (US) for international business machines corporation
IPC Code(s): H10N70/00, H10B63/00
CPC Code(s): H10N70/8833
Abstract: a memory structure that includes a dielectric stack of a ferroelectric dielectric layer and a paraelectric dielectric layer. at least the ferroelectric dielectric layer produces a negative capacitance to amplify an applied voltage. a thickness of the ferroelectric dielectric layer and the paraelectric dielectric layer results in simultaneous breakdown of a dielectric material in each of the ferroelectric dielectric layer and the paraelectric dielectric layer for the formation of conductive filaments upon being exposed to an electric field produced by the applied voltage amplified by the negative capacitance. the memory structure also includes a first electrode at a first end of the dielectric stack, and a second electrode at a second end of the dielectric stack. the applied voltage is applied to the memory structure through at least one of the first electrode and the second electrode.
International Business Machines Corporation patent applications on October 17th, 2024
- International Business Machines Corporation
- G05B19/042
- CPC G05B19/042
- International business machines corporation
- G06F9/4401
- G06F9/455
- CPC G06F9/442
- CPC G06F9/45558
- G06F9/50
- CPC G06F9/5077
- G06F9/54
- CPC G06F9/541
- G06F17/11
- CPC G06F17/11
- G06F30/27
- CPC G06F30/27
- G06F40/166
- G06F16/23
- G06F16/958
- G06F40/14
- G06F40/197
- G06F40/30
- CPC G06F40/166
- G06N3/049
- G06N3/08
- CPC G06N3/049
- G06Q30/04
- CPC G06N3/08
- G06N5/022
- G06F16/901
- CPC G06N5/022
- G06N10/40
- CPC G06N10/40
- G06N20/20
- CPC G06N20/20
- G06T7/00
- G06T5/00
- CPC G06T7/0002
- G06T7/13
- G06F17/16
- G11C13/00
- CPC G06T7/13
- G06V20/56
- A47L9/00
- A47L9/28
- G05D1/00
- G06V10/70
- G06V20/17
- CPC G06V20/56
- G10L15/22
- G10L15/02
- CPC G10L15/22
- H01L23/48
- H01L21/8234
- H01L27/088
- H01L29/06
- H01L29/423
- H01L29/66
- H01L29/775
- H01L29/786
- CPC H01L23/481
- H01L23/00
- H01L23/373
- H01L23/473
- CPC H01L24/32
- CPC H01L27/088
- H03L7/18
- H03B5/12
- CPC H03L7/18
- H04L12/18
- CPC H04L12/1831
- H04L9/40
- G06F21/53
- CPC H04L63/1416
- H04W64/00
- H04B17/318
- H04L41/16
- CPC H04W64/00
- H05K7/20
- CPC H05K7/20272
- H10N50/80
- G11C11/16
- H01F10/32
- H01F41/34
- H10B61/00
- H10N50/01
- H10N50/85
- CPC H10N50/80
- H10N70/00
- H10B63/00
- CPC H10N70/8833
