Intel corporation (20240332403). STACKED TRANSISTORS simplified abstract
Contents
STACKED TRANSISTORS
Organization Name
Inventor(s)
Patrick Morrow of Portland OR (US)
Rishabh Mehandru of Portland OR (US)
Aaron D. Lilak of Beaverton OR (US)
STACKED TRANSISTORS - A simplified explanation of the abstract
This abstract first appeared for US patent application 20240332403 titled 'STACKED TRANSISTORS
Simplified Explanation: The patent application describes a process where an interconnect layer is bonded to a substrate, with subsequent layers and openings formed to expose and create contact regions on specific portions of the device layer.
Key Features and Innovation:
- Deposition of interconnect layer on device layers on substrates
- Formation of insulating layers and openings to expose device layers
- Creation of contact regions on exposed device layers
Potential Applications: This technology could be applied in semiconductor manufacturing, integrated circuit fabrication, and microelectronics industries.
Problems Solved: This technology addresses the need for precise and controlled contact regions on device layers in semiconductor devices.
Benefits: The benefits of this technology include improved performance, reliability, and efficiency of semiconductor devices.
Commercial Applications: Potential commercial applications include the production of advanced electronic devices, such as smartphones, computers, and other consumer electronics.
Prior Art: Readers can explore prior art related to this technology in the field of semiconductor device fabrication, interconnect technologies, and integrated circuit design.
Frequently Updated Research: Stay updated on the latest advancements in semiconductor manufacturing, device integration, and interconnect technologies for potential improvements in this field.
Questions about the Technology: 1. What are the specific materials used in the interconnect layer bonding process? 2. How does this technology compare to traditional methods of creating contact regions on device layers?
Original Abstract Submitted
a first interconnect layer is bonded to a first substrate. the first interconnect layer is deposited on a first device layer on a second device layer on a second substrate. the second device layer is revealed from the second substrate side. a first insulating layer is deposited on the revealed second device layer. a first opening is formed in the first insulating layer to expose a first portion of the second device layer. a contact region is formed on the exposed first portion of the second device layer.
