Intel corporation (20240332125). 2D FILLERS FOR REDUCED CTE FOR PID simplified abstract

2D FILLERS FOR REDUCED CTE FOR PID

Organization Name

intel corporation

Inventor(s)

Kyle Arrington of Gilbert AZ (US)

Clay Arrington of Queen Creek AZ (US)

Bohan Shan of Chandler AZ (US)

Haobo Chen of Gilbert AZ (US)

Srinivas V. Pietambaram of Chandler AZ (US)

Gang Duan of Chandler AZ (US)

Ziyin Lin of Chandler AZ (US)

Hongxia Feng of Chandler AZ (US)

Yiqun Bai of Chandler AZ (US)

Xiaoying Guo of Chandler AZ (US)

Dingying Xu of Chandler AZ (US)

Bai Nie of Chandler AZ (US)

2D FILLERS FOR REDUCED CTE FOR PID - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240332125 titled '2D FILLERS FOR REDUCED CTE FOR PID

The patent application describes a package substrate with a first layer and a second layer containing a dielectric material with sulfur and fillers with a volume fraction less than 0.2.

• Simplified Explanation:

- The patent application discusses a package substrate with two layers, one containing a dielectric material with sulfur and fillers. - The fillers have a volume fraction of less than 0.2.

• Key Features and Innovation:

- Package substrate with two layers. - Second layer contains dielectric material with sulfur. - Fillers with volume fraction less than 0.2.

• Potential Applications:

- Electronics packaging. - Semiconductor devices.

• Problems Solved:

- Improved insulation. - Enhanced performance of electronic components.

• Benefits:

- Better thermal management. - Increased reliability of electronic devices.

• Commercial Applications:

- Potential use in the semiconductor industry for advanced packaging solutions.

• Questions about the Technology:

1. How does the presence of sulfur in the dielectric material impact the performance of the package substrate? 2. What are the advantages of using fillers with a volume fraction less than 0.2 in the second layer of the package substrate?

• Frequently Updated Research:

- Ongoing research on the optimization of fillers in dielectric materials for electronic packaging applications.

Original Abstract Submitted

embodiments disclosed herein include a package substrate. in an embodiment, the package substrate comprises a first layer and a second layer over the first layer. in an embodiment, the second layer comprises a dielectric material including sulfur. in an embodiment, fillers are within the second layer. in an embodiment, the fillers have a volume fraction that is less than approximately 0.2.