Intel Corporation patent applications on October 17th, 2024

Patent Applications by Intel Corporation on October 17th, 2024

Intel Corporation: 37 patent applications

Intel Corporation has applied for patents in the areas of H01L29/06 (4), H01L25/065 (4), G06F9/30 (4), H01L29/66 (4), H04L9/40 (3) B60R25/30 (1), H01L29/517 (1), H01L23/535 (1), H01L25/0657 (1), H01L27/0924 (1)

With keywords such as: gate, device, data, based, memory, apparatus, circuit, circuitry, surface, and layer in patent application abstracts.

Patent Applications by Intel Corporation

20240343222. MULTI-MODAL CONTEXT BASED VEHICLE THEFT PREVENTION_simplified_abstract_(intel corporation)

Inventor(s): Tamir D. Munafo of Naale (IL) for intel corporation, Lital Shiryan of Ramat Gan (IL) for intel corporation, Yuli Barcohen of Nokdim (IL) for intel corporation, Varada Tarun Rao of Folsom CA (US) for intel corporation, Suraj Sindia of Hillsboro OR (US) for intel corporation

IPC Code(s): B60R25/30, B60R25/24, B60R25/25, G06F21/31, G06F21/88, G06N3/042, G06N3/08, G06N3/088, G06N5/046, G06N7/01

CPC Code(s): B60R25/30

Abstract: a motor vehicle management system provides theft prevention based on contextual information. the motor vehicle management platform includes sensing equipment that can provide input data to determine a context of the vehicle and an operator of the vehicle. the context can include location information of the motor vehicle and an identity of the operator of the motor vehicle. based on permissions for the operator, the system can determine if a context of the vehicle violates permissions for the identified operator.

20240345319. MULTI-LAYER SILICON PHOTONICS APPARATUS_simplified_abstract_(intel corporation)

Inventor(s): Hari Mahalingam of San Jose CA (US) for intel corporation, Harel Frish of Albuquerque NM (US) for intel corporation, Sean McCargar of Rio Ranch NM (US) for intel corporation, Joshua Keener of Albuquerque NM (US) for intel corporation, Shane Yerkes of Placitas NM (US) for intel corporation, John Heck of Berkeley CA (US) for intel corporation, Ling Liao of Santa Clara CA (US) for intel corporation

IPC Code(s): G02B6/122, G02B6/13, G02B6/26, G02B6/30

CPC Code(s): G02B6/1228

Abstract: embodiments of the present disclosure are directed to low numerical aperture (na) optical couplers, or spot size converters, that include a lateral taper section and/or a vertical adiabatic taper section. in embodiments, the optical couplers may be positioned on a silicon substrate proximate to v-grooves within the substrate to contain optical fibers to self-align and to couple with the optical couplers. other embodiments may be described and/or claimed.

20240345324. OPTICAL FIBER MOUNTS FOR PRINTED CIRCUIT BOARDS AND INTEGRATED CIRCUIT DEVICE PACKAGES_simplified_abstract_(intel corporation)

Inventor(s): Benjamin Duong of Phoenix AZ (US) for intel corporation, Kristof Darmawikarta of Chandler AZ (US) for intel corporation, Soham Agarwal of Chandler AZ (US) for intel corporation, Marcel Said of Beaverton OR (US) for intel corporation, Sandeep Gaan of Phoenix AZ (US) for intel corporation

IPC Code(s): G02B6/26

CPC Code(s): G02B6/26

Abstract: an integrated circuit package includes a substrate with an integrated circuit device mounting surface, and at least one optical fiber mount in the substrate. the optical fiber mount includes a support having at least one optical fiber mounting channel, and the optical fiber mounting channel is configured to mount at least one clad optical fiber.

20240345345. SYSTEM, APPARATUS, AND METHOD OF LINK TRAINING OVER A REDRIVER-BASED OPTICAL INTERCONNECT_simplified_abstract_(intel corporation)

Inventor(s): Debendra Das Sharma of Saratoga CA (US) for intel corporation

IPC Code(s): G02B6/42, G02B6/43

CPC Code(s): G02B6/4274

Abstract: for example, an electronic system may include interconnect circuitry to communicate over an electrical interconnect; and a physical layer (phy) controller configured to access a plurality of optical-capability registers to identify optical-training control information and optical-capability information. for example, the optical-training control information may include a start-training bit. for example, based on a determination that the start-training bit is set to a predefined value, the phy controller may initiate an optical-based link training procedure via the electrical interconnect to train a link between the electronic system and a partner electronic system over a redriver-based optical interconnect. for example, the optical-based link training procedure may be based on the optical-capability information.

20240345639. FLEXIBLE AND MODULAR TOP AND BOTTOM SIDE PROCESSOR UNIT MODULE COOLING_simplified_abstract_(intel corporation)

Inventor(s): Andres Ramirez Macias of Zapopan (MX) for intel corporation, Aardra B. Athalye of Beaverton OR (US) for intel corporation, Devdatta Prakash Kulkarni of Portland OR (US) for intel corporation, Gilberto Rayas Paredes of Zapopan (MX) for intel corporation, Bijoyraj Sahu of Portland OR (US) for intel corporation

IPC Code(s): G06F1/20, H05K1/02

CPC Code(s): G06F1/206

Abstract: flexible and modular top and bottom side processor unit module cooling is disclosed. an example apparatus comprises a printed circuit board including an integrated circuit component on a first side of the printed circuit board, and an electronic component on a second side of the printed circuit board, the second side facing away from the first side; a stiffener to at least partially enclose the printed circuit board, and a flexible strap to thermally couple the electronic component and a portion of the stiffener, the portion of the stiffener positioned adjacent the first side of the printed circuit board.

20240345804. Floating-Point Dynamic Range Expansion_simplified_abstract_(intel corporation)

Inventor(s): Bogdan Mihai Pasca of Toulouse (FR) for intel corporation, Martin Langhammer of High Wycombe (GB) for intel corporation

IPC Code(s): G06F7/487, G06F7/544

CPC Code(s): G06F7/4876

Abstract: the present disclosure relates generally to techniques for adjusting the number representation (e.g., format) of a variable before and/or after performing one or more arithmetic operations on the variable. in particular, the present disclosure relates to scaling the range of a variable to a suitable representation based on available hardware (e.g., hard logic) in an integrated circuit device. for example, an input in a first number format (e.g., bfloat16) may be scaled to a second number format (e.g., half-precision floating-point) so that circuitry implemented to receive inputs in the second number format may perform one or more arithmetic operations on the input. further, the output produced by the circuitry may be scaled back to the first number format. accordingly, arithmetic operations, such as a dot-product, performed in a first format may be emulated by scaling the inputs to and/or the outputs from arithmetic operations performed in another format.

20240345839. PROCESSING PIPELINE WITH ZERO LOOP OVERHEAD_simplified_abstract_(intel corporation)

Inventor(s): Kameran Azadet of San Ramon CA (US) for intel corporation, Jeroen Leijten of Hulsel (NL) for intel corporation, Joseph Williams of Holmdel NJ (US) for intel corporation

IPC Code(s): G06F9/30, G06F9/38, G06F9/46, G06F9/54

CPC Code(s): G06F9/30036

Abstract: techniques are disclosed for reducing or eliminating loop overhead caused by function calls in processors that form part of a pipeline architecture. the processors in the pipeline process data blocks in an iterative fashion, with each processor in the pipeline completing one of several iterations associated with a processing loop for a commonly-executed function. the described techniques leverage the use of message passing for pipelined processors to enable an upstream processor to signal to a downstream processor when processing has been completed, and thus a data block is ready for further processing in accordance with the next loop processing iteration. the described techniques facilitate a zero loop overhead architecture, enable continuous data block processing, and allow the processing pipeline to function indefinitely within the main body of the processing loop associated with the commonly-executed function where efficiency is greatest.

20240345841. SYSTEM, APPARATUS AND METHOD FOR FINE-GRAIN ADDRESS SPACE SELECTION IN A PROCESSOR_simplified_abstract_(intel corporation)

Inventor(s): UTKARSH Y. KAKAIYA of Folsom CA (US) for intel corporation, RAJESH SANKARAN of Portland OR (US) for intel corporation, GILBERT NEIGER of Portland OR (US) for intel corporation, PHILIP LANTZ of Cornelius OR (US) for intel corporation, SANJAY K. KUMAR of Hillsboro OR (US) for intel corporation

IPC Code(s): G06F9/34, G06F9/30, G06F12/109

CPC Code(s): G06F9/34

Abstract: in one embodiment, a processor comprises: a first configuration register to store a pointer to a process address space identifier (pasid) table; and an execution circuit coupled to the first configuration register. the execution circuit, in response to a first instruction, is to obtain command data from a first location identified in a source operand of the first instruction, obtain a pasid table handle from the command data, access a first entry of the pasid table using the pointer from the first configuration register and the pasid table handle to obtain a pasid value, insert the pasid value into the command data, and send the command data to a device coupled to the processor. other embodiments are described and claimed.

20240345865. TECHNIQUES FOR VIRTUAL MACHINE TRANSFER AND RESOURCE MANAGEMENT_simplified_abstract_(intel corporation)

Inventor(s): SANJAY KUMAR of Hillsboro OR (US) for intel corporation, PHILIP R. LANTZ of Cornelius OR (US) for intel corporation, KUN TIAN of Shanghai (CN) for intel corporation, UTKARSH Y. KAKAIYA of El Dorado Hills CA (US) for intel corporation, RAJESH M. SANKARAN of Portland OR (US) for intel corporation

IPC Code(s): G06F9/455, G06F9/30, G06F12/1009

CPC Code(s): G06F9/45558

Abstract: techniques for transferring virtual machines and resource management in a virtualized computing environment are described. in one embodiment, for example, an apparatus may include at least one memory, at least one processor, and logic for transferring a virtual machine (vm), at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one processor, the logic to generate a plurality of virtualized capability registers for a virtual device (vdev) by virtualizing a plurality of device-specific capability registers of a physical device to be virtualized by the vm, the plurality of virtualized capability registers comprising a plurality of device-specific capabilities of the physical device, determine a version of the physical device to support via a virtual machine monitor (vmm), and expose a subset of the virtualized capability registers associated with the version to the vm. other embodiments are described and claimed.

20240345969. DYNAMICALLY INSERT TIMING AND VOLTAGE OFFSET CONTROL (VOC) OFFSETS IN INPUT/OUTPUT (IO) DURING FUNCTIONAL TRAFFIC_simplified_abstract_(intel corporation)

Inventor(s): Diyanesh Babu CHINNAKKONDA VIDYAPOORNACHARY of Austin TX (US) for intel corporation, Tonia M. ROSE of Wendell NC (US) for intel corporation

IPC Code(s): G06F13/16

CPC Code(s): G06F13/1668

Abstract: a memory subsystem includes a memory space reserved for margining traffic. the memory controller sets a rank bit to select the reserved memory space and configures a physical interface with different settings to test. thus, the system can have operational io (input/output) settings and margining io settings that can both be used at runtime. if the margining io settings provide an improved error rate over the operational io settings, the memory controller can reconfigure the operation io settings.

20240345990. Multi-tile Memory Management for Detecting Cross Tile Access Providing Multi-Tile Inference Scaling and Providing Page Migration_simplified_abstract_(intel corporation)

Inventor(s): Lakshminarayanan Striramassarma of Folsom CA (US) for intel corporation, Prasoonkumar Surti of Folsom CA (US) for intel corporation, Varghese George of Folsom CA (US) for intel corporation, Ben Ashbaugh of Folsom CA (US) for intel corporation, Aravindh Anantaraman of Folsom CA (US) for intel corporation, Valentin Andrei of San Jose CA (US) for intel corporation, Abhishek Appu of El Dorado Hills CA (US) for intel corporation, Nicolas Galoppo Von Borries of Portland OR (US) for intel corporation, Altug Koker of El Dorado Hills CA (US) for intel corporation, Mike Macpherson of Portland OR (US) for intel corporation, Subramaniam Maiyuran of Gold River CA (US) for intel corporation, Nilay Mistry of Bangalore (IN) for intel corporation, Elmoustapha Ould-Ahmed-Vall of Chandler AZ (US) for intel corporation, Selvakumar Panneer of Portland OR (US) for intel corporation, Vasanth Ranganathan of El Dorado Hills CA (US) for intel corporation, Joydeep Ray of Folsom CA (US) for intel corporation, Ankur Shah of Folsom CA (US) for intel corporation, Saurabh Tangri of Folsom CA (US) for intel corporation

IPC Code(s): G06F15/78, G06F7/544, G06F7/575, G06F7/58, G06F9/30, G06F9/38, G06F9/50, G06F12/02, G06F12/06, G06F12/0802, G06F12/0804, G06F12/0811, G06F12/0862, G06F12/0866, G06F12/0871, G06F12/0875, G06F12/0882, G06F12/0888, G06F12/0891, G06F12/0893, G06F12/0895, G06F12/0897, G06F12/1009, G06F12/128, G06F15/80, G06F17/16, G06F17/18, G06N3/08, G06T1/20, G06T1/60, G06T15/06, H03M7/46

CPC Code(s): G06F15/7839

Abstract: multi-tile memory management for detecting cross tile access, providing multi-tile inference scaling with multicasting of data via copy operation, and providing page migration are disclosed herein. in one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (gpu) having a memory and a memory controller, a second graphics processing unit (gpu) having a memory and a cross-gpu fabric to communicatively couple the first and second gpus. the memory controller is configured to determine whether frequent cross tile memory accesses occur from the first gpu to the memory of the second gpu in the multi-gpu configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first gpu to the memory of the second gpu.

20240345995. APPARATUS, METHOD AND COMPUTER PROGRAM FOR ACCESSING AN APPLICATION SOFTWARE BY A PLURALITY OF USERS_simplified_abstract_(intel corporation)

Inventor(s): Juguang ZHENG of Shanghai (CN) for intel corporation

IPC Code(s): G06F16/185, G06F8/65

CPC Code(s): G06F16/185

Abstract: an apparatus for accessing an application software by a plurality of users is disclosed. the apparatus comprises a physical storage medium. the physical storage medium comprises a lower directory tree and a plurality of user-specific upper directory trees. the apparatus comprises processing circuitry configured to store the application software in the lower directory tree, and, for each of the plurality of users, mount a respective overlay filesystem overlaying the respective user-specific upper directory tree over the lower directory tree. in some examples, the apparatus may be a cloud gaming server. the application software may be a computer game for cloud gaming.

20240346206. APPARATUS AND METHOD FOR QUANTUM COMPUTING PERFORMANCE SIMULATION_simplified_abstract_(intel corporation)

Inventor(s): Anne MATSUURA of Portland OR (US) for intel corporation, Sonika JOHRI of Portland OR (US) for intel corporation, Justin HOGABOAM of Aloha OR (US) for intel corporation

IPC Code(s): G06F30/20, G06N10/00

CPC Code(s): G06F30/20

Abstract: apparatus and method for a full quantum system simulator. for example, one embodiment of a method comprises: initializing a quantum computing system simulator for simulating multiple layers of a quantum system including one or more non-quantum layers and one or more physical quantum device layers of the quantum system; simulating a first set of operations of the one or more non-quantum layers of the quantum system to generate first simulation results; simulating a second set of operations of the one or more quantum device layers of the quantum system to generate second simulation results; analyzing the first and second simulation results to provide at least one configuration recommendation for the quantum system.

20240346341. METHOD AND APPARATUS FOR FUSING LAYERS OF DIFFERENT MODELS_simplified_abstract_(intel corporation)

Inventor(s): Guangming CHEN of Shanghai (CN) for intel corporation, Renzhi JIANG of Shanghai (CN) for intel corporation, Fengyi SUN of Shanghai (CN) for intel corporation, Zhengxu HUANG of Shanghai (CN) for intel corporation, Jingxuan DONG of Shanghai (CN) for intel corporation

IPC Code(s): G06N5/022

CPC Code(s): G06N5/022

Abstract: the disclosure relates to method and apparatus for fusing layers of different models. the method for fusing layers of different models comprises: searching layers from different models and determining whether to perform layer fusing; fusing instructions in the layers from different models into a fused instruction in response to determining to perform layer fusing; combining input data for the instructions in the layers from different models into a combined input data; allocating a continuous storage area in a memory for the combined input data; loading the combined input data for the fused instruction from the continuous storage area in the memory to perform the fused instruction; and storing output data obtained after performing the fused instruction into a continuous storage area in the memory.

20240346348. APPARATUS AND METHOD INCLUDING SCALABLE REPRESENTATIONS OF ARBITRARY QUANTUM COMPUTING ROTATIONS_simplified_abstract_(intel corporation)

Inventor(s): XIANG ZOU of Hillsboro OR (US) for intel corporation, SHAVINDRA PREMARATNE of Portland OR (US) for intel corporation

IPC Code(s): G06N10/00

CPC Code(s): G06N10/00

Abstract: apparatus and method for performing a quantum rotation operation. for example, one embodiment of an apparatus comprises: a decoder to decode a plurality of instructions; execution circuitry to execute a first instruction or first set of the instructions to generate a floating point (fp) value and to store the fp value in a first register; the execution circuitry to execute a second instruction or second set of the one or more of the instructions to read the fp value from the first register and compress the fp value to generate a compressed fp value having a precision selected for performing quantum rotation operations; and quantum interface circuitry to process the compressed fp value to cause a quantum rotation to be performed on one or more qubits of a quantum processor.

20240346801. MEASURING OBJECT PECULIARITY IN DISTRIBUTED ENVIRONMENTS_simplified_abstract_(intel corporation)

Inventor(s): Priyanka Mudgal of Portland OR (US) for intel corporation, Rita Hanna Wouhaybi of Portland OR (US) for intel corporation, Caleb Mark McMillan of Forest Grove OR (US) for intel corporation, Patrick L. Connor of Beaverton OR (US) for intel corporation, Ritesh Kumar Rajore of Bangalore (IN) for intel corporation, Jennifer Marie Williams of Hillsboro OR (US) for intel corporation

IPC Code(s): G06V10/44

CPC Code(s): G06V10/44

Abstract: example apparatus disclosed herein are to generate first descriptive data of a first physical characteristic of a first object based on first camera sensor data from a first camera sensor, and generate second descriptive data of a second physical characteristic of a second object based on second camera sensor data from a second camera sensor different from the first camera sensor. disclosed example apparatus are also identify, based on the first descriptive data and the second descriptive data, common physical characteristics associated with both the first object and the second object, first unique physical characteristics associated with the first object, and second unique physical characteristics associated with the second object. disclosed example apparatus are further to identify the first object and the second object as one of a same object or different objects based on the common physical characteristics, the first unique physical characteristics, and the second unique physical characteristics.

20240346809. PROCEDURAL VIDEO ASSESSMENT_simplified_abstract_(intel corporation)

Inventor(s): Ping GUO of Beijing (CN) for intel corporation, Mee Sim LAI of Penang (MY) for intel corporation, Kuan Heng LEE of Ayer Itam (MY) for intel corporation, Wee Hoo CHEAH of Taipei, Taiwan (CN) for intel corporation, Jason GARCIA of Scottsdale AZ (US) for intel corporation, Liang QIU of Shanghai (CN) for intel corporation, Peng WANG of Beijing (CN) for intel corporation, Jiajie WU of Shanghai (CN) for intel corporation, Xiangbin WU of Beijing (CN) for intel corporation

IPC Code(s): G06V10/776, G06V10/70, G06V10/77, G06V10/774, G06V10/82, G06V20/40, G09B19/00

CPC Code(s): G06V10/776

Abstract: the application provides an apparatus and a method for procedural video assessment. the apparatus includes: interface circuitry; and processor circuitry coupled to the interface circuitry and configured to: perform an action segmentation process for a procedural video received via the interface circuitry to obtain a plurality of action features associated with the procedure video; transform the plurality of action features into a plurality of action-procedure features based on an action-procedure relationship learning module for discovering a relationship between the plurality of action features and a plurality of scoring oriented procedures associated with the procedure video; and perform a procedure classification process to infer the plurality of scoring oriented procedures from the plurality of action-procedure features.

20240346979. Optimized Display Image Rendering_simplified_abstract_(intel corporation)

Inventor(s): Atsuo Kuwahara of Hillsboro OR (US) for intel corporation, Deepak S. Vembar of Portland OR (US) for intel corporation, Paul S. Diefenbaugh of Portland OR (US) for intel corporation, Vallabhajosyula S. Somayazulu of Portland OR (US) for intel corporation, Kofi C. Whitney of Hillsboro OR (US) for intel corporation

IPC Code(s): G09G3/20, G06F3/01, G06F3/147

CPC Code(s): G09G3/2096

Abstract: in one example, a head mounted display system includes at least one memory; and at least one processor to execute instructions to: detect a first position and a first view direction of a head of a user based on sensor data generated by at least one of an accelerometer, at least one camera, or a gyroscope at a first point in time; determine a latency associated with a time to cause an image to be presented on the display; determine a predicted position and a predicted view direction of the head of the user at a second point in time based on the latency; render, prior to the second point in time, the image for presentation on the display based on the predicted position and the predicted view direction of the head of the user; and cause the display to present the rendered image.

20240347394. INTEGRATED CIRCUITS WITH RECESSED GATE ELECTRODES_simplified_abstract_(intel corporation)

Inventor(s): Srijit MUKHERJEE of Portland OR (US) for intel corporation, Christopher J. WIEGAND of Portland OR (US) for intel corporation, Tyler J. WEEKS of Hillsboro OR (US) for intel corporation, Mark Y. LIU of West Linn OR (US) for intel corporation, Michael L. HATTENDORF of Portland OR (US) for intel corporation

IPC Code(s): H01L21/8238, H01L21/28, H01L21/8234, H01L27/088, H01L27/092, H01L29/49, H01L29/66, H10B10/00

CPC Code(s): H01L21/82385

Abstract: integrated circuits including mosfets with selectively recessed gate electrodes. transistors having recessed gate electrodes with reduced capacitive coupling area to adjacent source and drain contact metallization are provided alongside transistors with gate electrodes that are non-recessed and have greater z-height. in embodiments, analog circuits employ transistors with gate electrodes of a given z-height while logic gates employ transistors with recessed gate electrodes of lesser z-height. in embodiments, subsets of substantially planar gate electrodes are selectively etched back to differentiate a height of the gate electrode based on a given transistor's application within a circuit.

20240347402. METHODS AND APPARATUS TO REDUCE DELAMINATION IN HYBRID CORES_simplified_abstract_(intel corporation)

Inventor(s): Jeremy Ecton of Gilbert AZ (US) for intel corporation, Brandon Christian Marin of Gilbert AZ (US) for intel corporation, Srinivas Venkata Ramanuja Pietambaram of Chandler AZ (US) for intel corporation, Gang Duan of Chandler AZ (US) for intel corporation, Leonel Arana of Phoenix AZ (US) for intel corporation, Benjamin Duong of Phoenix AZ (US) for intel corporation

IPC Code(s): H01L23/13, H01L23/15, H01L25/065

CPC Code(s): H01L23/13

Abstract: methods and apparatus to reduce delamination in hybrid cores are disclosed. an example hybrid core of an integrated circuit (ic) package comprises a frame, and a glass panel including a top surface, an edge adjacent the frame, and a tapered surface extending between the edge and the top surface.

20240347457. PITCH TRANSLATION ARCHITECTURE FOR SEMICONDUCTOR PACKAGE INCLUDING EMBEDDED INTERCONNECT BRIDGE_simplified_abstract_(intel corporation)

Inventor(s): Andrew COLLINS of Chandler AZ (US) for intel corporation, Bharat P. PENMECHA of Phoenix AZ (US) for intel corporation, Rajasekaran SWAMINATHAN of Chandler AZ (US) for intel corporation, Ram VISWANATH of Phoenix AZ (US) for intel corporation

IPC Code(s): H01L23/528, H01L23/00, H01L23/498, H01L23/538, H01L25/065, H01L25/18

CPC Code(s): H01L23/5283

Abstract: various embodiments relate to a semiconductor package. the semiconductor package includes a first die. the first die includes a first bridge interconnect region. the semiconductor package further includes a second die. the second die includes a second bridge interconnect region. the semiconductor package includes a bridge die. the bridge die includes a first contact area to connect to the first bridge interconnect region and a second contact area to connect to the second bridge interconnect region. in the semiconductor package, the first bridge interconnect region is larger than the second bridge interconnect region. additionally, each of the first bridge interconnect region and the second bridge interconnect region include a plurality of conductive bumps. an average pitch between adjacent bumps of the first bridge interconnect region is larger than an average pitch between adjacent bumps of the second bridge interconnect region.

20240347465. CONTACT OVER ACTIVE GATE STRUCTURES WITH ETCH STOP LAYERS FOR ADVANCED INTEGRATED CIRCUIT STRUCTURE FABRICATION_simplified_abstract_(intel corporation)

Inventor(s): Atul MADHAVAN of Portland OR (US) for intel corporation, Nicholas J. KYBERT of Portland OR (US) for intel corporation, Mohit K. HARAN of Hillsboro OR (US) for intel corporation, Hiten KOTHARI of Beaverton OR (US) for intel corporation

IPC Code(s): H01L23/535, H01L21/02, H01L21/027, H01L21/311, H01L21/768, H01L21/8234, H01L27/088, H01L29/45, H01L29/51

CPC Code(s): H01L23/535

Abstract: contact over active gate (coag) structures with etch stop layers, and methods of fabricating contact over active gate (coag) structures using etch stop layers, are described. in an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. a plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a trench insulating layer thereon. a first dielectric etch stop layer is directly on and continuous over the trench insulating layers and the gate insulating layers. a second dielectric etch stop layer is directly on and continuous over the first dielectric etch stop layer, the second dielectric etch stop layer distinct from the first dielectric etch stop layer. an interlayer dielectric material is on the second dielectric etch stop layer.

20240347514. STACKED DIE NETWORK INTERFACE CONTROLLER CIRCUITRY_simplified_abstract_(intel corporation)

Inventor(s): Naveed Zaman of Saratoga CA (US) for intel corporation, Aravind Dasu of Milpitas CA (US) for intel corporation, Sreedhar Ravipalli of Cupertino CA (US) for intel corporation, Rakesh Cheerla of Cupertino CA (US) for intel corporation, Martin Home of Alamo CA (US) for intel corporation

IPC Code(s): H01L25/065, H04L9/40, H04L47/10, H04L49/90

CPC Code(s): H01L25/0657

Abstract: a smart network interface controller (nic) implemented using a stacked die configuration is provided. the nic may include user-customizable networking circuits formed in a top programmable die and primitive network function blocks formed in a bottom application-specific integrated circuit (asic) die. the top programmable die may provide a flexible packet processing pipeline to facilitate efficient control and data communication between the user-customizable networking circuits and the primitive network function blocks. the bottom asic die may also include an array of memory blocks operable as lookup tables and intermediate buffers for other network processing circuitry in the nic. a nic configured in this way provides both performance, power, and area benefits and superior customer configurability.

20240347539. INTEGRATED CIRCUIT STRUCTURES HAVING CUT METAL GATES_simplified_abstract_(intel corporation)

Inventor(s): Tahir GHANI of Portland OR (US) for intel corporation, Mohit K. HARAN of Hillsboro OR (US) for intel corporation, Mohammad HASAN of Aloha OR (US) for intel corporation, Biswajeet GUHA of Hillsboro OR (US) for intel corporation, Alison V. DAVIS of Portland OR (US) for intel corporation, Leonard P. GULER of Hillsboro OR (US) for intel corporation

IPC Code(s): H01L27/092, H01L29/06, H01L29/66, H01L29/78

CPC Code(s): H01L27/0924

Abstract: integrated circuit structures having cut metal gates, and methods of fabricating integrated circuit structures having cut metal gates, are described. for example, an integrated circuit structure includes a fin having a portion protruding above a shallow trench isolation (sti) structure. a gate dielectric material layer is over the protruding portion of the fin and over the sti structure. a conductive gate layer is over the gate dielectric material layer. a conductive gate fill material is over the conductive gate layer. a dielectric gate plug is laterally spaced apart from the fin, the dielectric gate plug on but not through the sti structure. the gate dielectric material layer and the conductive gate layer are not along sides of the dielectric gate plug, and the conductive gate fill material is in contact with the sides of the dielectric gate plug.

20240347590. METHODS AND APPARATUS TO REDUCE STRESS IN INTEGRATED CIRCUIT PACKAGES_simplified_abstract_(intel corporation)

Inventor(s): Bhaskar Jyoti Krishnatreya of Hillsboro OR (US) for intel corporation, Guruprasad Arakere of Chandler AZ (US) for intel corporation, Nitin Ashok Deshpande of Chandler AZ (US) for intel corporation, Mohammad Enamul Kabir of Portland OR (US) for intel corporation, Omkar Gopalkrishna Karhade of Chandler AZ (US) for intel corporation, Keith Edward Zawadzki of Portland OR (US) for intel corporation, Trianggono S. Widodo of Hillsboro OR (US) for intel corporation

IPC Code(s): H01L29/06, H01L21/306, H01L21/3065, H01L21/78, H01L23/00, H01L25/065

CPC Code(s): H01L29/0657

Abstract: systems, apparatus, articles of manufacture, and methods to reduce stress in integrated circuit packages are disclosed. an example semiconductor chip includes: a front surface; a back surface opposite the front surface; a first lateral surface extending between the front surface and the back surface; a second lateral surface extending between the front surface and the back surface; and a curved fillet at an intersection between the first lateral surface and the second lateral surface.

20240347595. Cavity Spacer for Nanowire Transistors_simplified_abstract_(intel corporation)

Inventor(s): William HSU of Hillsboro OR (US) for intel corporation, Biswajeet GUHA of Hillsboro OR (US) for intel corporation, Leonard GULER of Hillsboro OR (US) for intel corporation, Souvik CHAKRABARTY of Hillsboro OR (US) for intel corporation, Jun Sung KANG of Portland OR (US) for intel corporation, Bruce BEATTIE of Portland OR (US) for intel corporation, Tahir GHANI of Portland OR (US) for intel corporation

IPC Code(s): H01L29/06, H01L21/8238, H01L29/423, H01L29/66, H01L29/78, B82Y10/00

CPC Code(s): H01L29/0673

Abstract: a transistor structure includes a base and a body over the base. the body comprises a semiconductor material and has a first end portion and a second end portion. a gate structure is wrapped around the body between the first end portion and the second end portion, where the gate structure includes a gate electrode and a dielectric between the gate electrode and the body. a source is in contact with the first end portion and a drain is in contact with the second end portion. a first spacer material is on opposite sides of the gate electrode and above the first end portion. a second spacer material is adjacent the gate structure and under the first end portion of the nanowire body. the second spacer material is below and in contact with a bottom surface of the source and the drain.

20240347610. CONTACT RESISTANCE REDUCTION IN TRANSISTOR DEVICES WITH METALLIZATION ON BOTH SIDES_simplified_abstract_(intel corporation)

Inventor(s): Koustav GANGULY of Beaverton OR (US) for intel corporation, Ryan KEECH of Portland OR (US) for intel corporation, Subrina RAFIQUE of Hillsboro OR (US) for intel corporation, Glenn A. GLASS of Portland OR (US) for intel corporation, Anand S. MURTHY of Portland OR (US) for intel corporation, Ehren MANNEBACH of Beaverton OR (US) for intel corporation, Mauro KOBRINSKY of Portland OR (US) for intel corporation, Gilbert DEWEY of Beaverton OR (US) for intel corporation

IPC Code(s): H01L29/417, H01L21/02, H01L21/285, H01L29/06, H01L29/423, H01L29/66, H01L29/786

CPC Code(s): H01L29/41733

Abstract: embodiments disclosed herein include transistor devices and methods of making such devices. in an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. in an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. in an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. in an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.

20240347618. SELF-ALIGNED GATE ENDCAP (SAGE) ARCHITECTURES WITH IMPROVED CAP_simplified_abstract_(intel corporation)

Inventor(s): Christine RADLINGER of Portland OR (US) for intel corporation, Tongtawee WACHARASINDHU of Hillsboro OR (US) for intel corporation, Andre BARAN of Portland OR (US) for intel corporation, Kiran CHIKKADI of Hillsboro OR (US) for intel corporation, Devin MERRILL of McMinnville OR (US) for intel corporation, Nilesh DENDGE of Hillsboro OR (US) for intel corporation, David J. TOWNER of Portland OR (US) for intel corporation, Christopher KENYON of Portland OR (US) for intel corporation

IPC Code(s): H01L29/51, H01L27/088, H01L29/423

CPC Code(s): H01L29/517

Abstract: self-aligned gate endcap (sage) architectures with improved caps, and methods of fabricating self-aligned gate endcap (sage) architectures with improved caps, are described. in an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. a second gate structure is over a second semiconductor fin. a gate endcap isolation structure is between the first gate structure and the second gate structure. the gate endcap isolation structure has a higher-k dielectric cap layer on a lower-k dielectric wall. the higher-k dielectric cap layer includes hafnium and oxygen and has 70% or greater monoclinic crystallinity.

20240347965. MAGNETIC CONNECTOR WITH ASYMMETRIC ATTACH/DETACH MECHANISM_simplified_abstract_(intel corporation)

Inventor(s): Samarth Alva of Bangalore (IN) for intel corporation, Jagadish Singh of Bangalore (IN) for intel corporation, Prakash Kurma Raju of Bangalore (IN) for intel corporation, Arvind S of Bangalore (IN) for intel corporation, Jun Liu of Shanghai (CN) for intel corporation, Vinaya Kumar Chandrasekhara of Portland OR (US) for intel corporation, Kasthuri Rangan Vijayasarathy of Bangalore (IN) for intel corporation, Anoop Parchuru of Bangalore (IN) for intel corporation, Smitha Kashyap Chandrachooda of Bangalore (IN) for intel corporation

IPC Code(s): H01R13/62, H01R13/64

CPC Code(s): H01R13/6205

Abstract: systems, apparatus, articles of manufacture, and methods are disclosed for magnetic connectors with asymmetric attach/detach mechanism. an example electronic device disclose herein includes a port having an opening to receive a connector and a magnet array associated with the port. the magnet array includes a first magnet, and a second magnet. the electronic device includes a spring to bias at least one of the first magnet or second magnet away from the opening.

20240348218. DUAL FEEDBACK CONTINUOUS TIME LINEAR EQUALIZER_simplified_abstract_(intel corporation)

Inventor(s): Saurabh ANMADWAR of Nagpur (IN) for intel corporation

IPC Code(s): H03F3/45

CPC Code(s): H03F3/45475

Abstract: an amplifier circuit, comprising an amplification stage, is configured to amplify an input signal, and to generate an output signal as the amplified input signal; a first feedback stage, configured to generate a first feedback voltage based on a voltage of the input signal, and to modify the output signal by the first feedback voltage; and a second feedback stage, configured to generate a second feedback voltage based on a current generated in response to the input signal, and to modify the output signal using the second feedback voltage.

20240348562. MULTI-HOST ISOLATION IN A SHARED NETWORKING PIPELINE_simplified_abstract_(intel corporation)

Inventor(s): Yotam Nizri of Mevaseret Tzion (IL) for intel corporation, Wing Cheung of Fremont CA (US) for intel corporation, Thang Quang Nguyen of Austin TX (US) for intel corporation, Kenneth Keels of Austin TX (US) for intel corporation, Noam Elati of Zichron Yaakov (IL) for intel corporation

IPC Code(s): H04L49/00, H04L49/9005

CPC Code(s): H04L49/3063

Abstract: a shared networking pipeline is implemented by a network interface device and shared by a plurality of host devices. a pool of shared buffers of a network interface device correspond to one or more stages in the pipeline and are configured to allocate entries to the plurality of host devices based on the respective shares of the shared packet processing pipeline. data is buffered associated with traffic of a first one of the plurality of host devices in a first subset of shared buffers, where the traffic is to proceed from a first stage to a second stage in the shared packet processing pipeline, and the data is associated with processing of the traffic by the second stage. forward progress of the traffic is to be prevented from the first stage to the second stage when the first subset of entries are occupied.

20240348622. TELEMETRY RESTRICTION MECHANISM_simplified_abstract_(intel corporation)

Inventor(s): Luis Kida of Beaverton OR (US) for intel corporation, Neerav Parikh of Hillsboro OR (US) for intel corporation, Reshma Lal of Portland OR (US) for intel corporation

IPC Code(s): H04L9/40

CPC Code(s): H04L63/105

Abstract: an apparatus comprising a network interface card (nic), including packet processing circuitry to determine whether the nic is to operate according to a first telemetry protection mode to prevent copying of packet data payloads for telemetry or a second telemetry protection mode to enable copying of packet payloads for telemetry.

20240348660. Hardware-based Zero Trust Network Access Agent for Improved Security_simplified_abstract_(intel corporation)

Inventor(s): Omer Ben-Shalom of Rishon Le-Tzion (IL) for intel corporation, Dan Horovitz of Rishon Le-Tzion (IL) for intel corporation, Ilil Blum Shem-Tov of Kiryat Tivon (IL) for intel corporation, Lev Faerman of Ramat Gan (IL) for intel corporation, Wissam Ghammashi of Carmiel (IL) for intel corporation

IPC Code(s): H04L9/40

CPC Code(s): H04L63/20

Abstract: hardware-based zero trust network access agents for improved security are disclosed herein. an example apparatus includes network interface circuitry; machine-readable instructions; and first processor circuitry programmable by the instructions to detect, via firmware execution, a request from a device to access a resource via a zero trust network access interface; determine, via the firmware execution, a security state of the device; and based on the security state of the device, transmit the request to a host operating system (os) via a virtual network interface, the operating system executed via second processor circuitry different than the first processor circuitry.

20240348801. ADAPTIVE GOP SIZE SELECTION_simplified_abstract_(intel corporation)

Inventor(s): Sebastian Possos of Sammamish WA (US) for intel corporation, Yi-jen Chiu of San Jose CA (US) for intel corporation, Ximin Zhang of San Jose CA (US) for intel corporation

IPC Code(s): H04N19/177, H04N19/136, H04N19/172

CPC Code(s): H04N19/177

Abstract: using a fixed group of pictures (gop) size in video encoding significantly hinders compression efficiency due to its inability to adapt to the dynamic nature of video content. while encoding leverages spatio-temporal redundancy within a gop for compression, a predetermined size fails to capture the varying complexity of scenes. this leads to wasted bits in low-motion segments and insufficient reference frame variation for high-motion areas, resulting in visual artifacts and reduced compression efficiency. to address this limitation, a gop size recommendation engine involving machine learning models can determine frame-level gop size recommendations based on pre-encoder frame statistics. the frame-level gop size recommendations are used to adapt the gop size for encoding video frames.

20240348806. POINT CLOUD CODING STANDARD CONFORMANCE DEFINITION IN COMPUTING ENVIRONMENTS_simplified_abstract_(intel corporation)

Inventor(s): Jill Boyce of Portland OR (US) for intel corporation

IPC Code(s): H04N19/196, H04N19/136, H04N19/42, H04N19/463, H04N19/70

CPC Code(s): H04N19/196

Abstract: a mechanism is described for facilitating defining of interoperability signaling and conformance points for the pcc standard in computing environments. a computing device of embodiments, as described herein, includes a decoder to decode a compressed bitstream of video data representing a point cloud, point cloud reconstructor circuitry to reconstruct a point cloud from the decoded patch video data, a syntax element parser to receive at least one syntax element representing interoperability signaling in the compressed bitstream to indicate the number of points in one or more pictures of the video data, and processing hardware to determine if the number of points in the one or more pictures of the compressed bitstream is within the conformance limits of the point cloud reconstructor circuitry.

20240349082. ENHANCED COLLABORATION BETWEEN USER EQUPIMENT AND NETWORK TO FACILITATE MACHINE LEARNING_simplified_abstract_(intel corporation)

Inventor(s): Ziyi LI of Beijing (CN) for intel corporation, Dawei YING of Portland OR (US) for intel corporation, Qian LI of Portland OR (US) for intel corporation, Zongrui DING of Portland OR (US) for intel corporation

IPC Code(s): H04W24/02, H04W60/04

CPC Code(s): H04W24/02

Abstract: this disclosure describes systems, methods, and devices related to collaboration between user equipment (ue) and network for machine learning. a radio access network (ran) node b device may transmit, to the ce device, an indication that the node b device supports machine learning; identify a service registration, received from the ue device, indicating that the ue device requests machine learning support from the node b device; transmit, to the ue device, a request for information associated with the ue device, the information associated with at least one of hardware capabilities or machine learning capabilities of the ue device; identify the information received from the ue based on the request for information; and transmit, to the ue device, a machine learning configuration for use by the ue device, wherein the machine learning configuration is based on the information.

20240349309. DCI ENHANCEMENTS FOR SOFT RESOURCE AVAILABILITY INDICATION_simplified_abstract_(intel corporation)

Inventor(s): Lili Wei of Portland OR (US) for intel corporation, Qian Li of Beaverton OR (US) for intel corporation

IPC Code(s): H04W72/29, H04W72/044, H04W72/232, H04W88/08

CPC Code(s): H04W72/29

Abstract: an apparatus for an integrated access and backhaul (iab) node includes processing circuitry coupled to a memory. to configure the iab node for resource availability indication in an iab network, configuration signaling received from a cu function of an iab donor node is decoded at a du function of the iab node. the configuration signaling configures a frequency-domain hard, soft, and not available (h/s/na) resource application for a plurality of resource types. dci received from a p-du function of a parent iab node is decoded at an mt function of the iab node. the dci includes an availability indicator for at least one soft resource region associated with the frequency-domain h/s/na resource application. a downlink transmission by the du function of the iab node to a c-mit function of a child iab node is configured using the at least one soft resource region based on the availability indicator.

Intel Corporation patent applications on October 17th, 2024