Category:Thomas Vogelsang of Mountain View CA (US)

Thomas Vogelsang of Mountain View CA (US)

Executive Summary

Thomas Vogelsang of Mountain View CA (US) is an inventor who has filed 8 patents. Their primary areas of innovation include {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} (3 patents), STATIC STORES (semiconductor memory devices (2 patents), Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating (2 patents), and they have worked with companies such as Rambus Inc. (8 patents). Their most frequent collaborators include (3 collaborations), (1 collaborations), (1 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• G11C11/4087 ({Address decoders, e.g. bit - or word line decoders; Multiple line decoders}): 3 patents
• G11C29/52 (STATIC STORES (semiconductor memory devices): 2 patents
• G11C11/4091 (Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating): 2 patents
• G06F3/0659 ({Command handling arrangements, e.g. command buffers, queues, command scheduling}): 2 patents
• G06F3/0673 ({Single storage device}): 2 patents
• G11C11/4093 (Input/output [I/O] data interface arrangements, e.g. data buffers): 2 patents
• G11C5/025 ({Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits,): 2 patents
• G11C11/4076 (Timing circuits (for regeneration management): 2 patents
• G11C11/4096 (Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches): 1 patents
• G06F3/0604 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 1 patents
• G06F3/0619 ({in relation to data integrity, e.g. data losses, bit errors}): 1 patents
• G06F3/0638 ({Organizing or formatting or addressing of data}): 1 patents
• G06F11/1076 ({Parity data used in redundant arrays of independent storages, e.g. in RAID systems}): 1 patents
• G11C7/1006 ({Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}): 1 patents
• G11C7/1009 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
• G11C7/1087 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
• G11C7/109 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
• G11C7/1093 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers): 1 patents
• G11C29/023 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C29/028 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C2029/0411 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C2207/107 (STATIC STORES (semiconductor memory devices): 1 patents
• H03M13/6312 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
• H03M13/159 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
• H03M13/43 (CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means): 1 patents
• G11C5/063 (STATIC STORES (semiconductor memory devices): 1 patents
• H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 1 patents
• H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H10B12/50 (ELECTRONIC MEMORY DEVICES): 1 patents
• H01L2225/06513 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06541 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06596 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/0002 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• G11C7/1039 ({using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}): 1 patents
• G11C7/08 (Control thereof): 1 patents
• G11C7/06 (Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}): 1 patents
• G11C7/065 (Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}): 1 patents
• G11C7/12 (STATIC STORES (semiconductor memory devices): 1 patents
• G11C7/222 (Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management): 1 patents
• G11C8/08 (Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines): 1 patents
• G11C8/10 (Decoders): 1 patents
• G06F3/061 (Digital input from, or digital output to, record carriers {, e.g. RAID, emulated record carriers or networked record carriers}): 1 patents
• G06F12/0895 (in hierarchically structured memory systems, e.g. virtual memory systems): 1 patents
• G11C8/18 (Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals): 1 patents
• G11C2207/2245 (STATIC STORES (semiconductor memory devices): 1 patents

Companies

List of Companies

• Rambus Inc.: 8 patents

Collaborators

• Frederick A. Ware of Los Altos Hills CA (US) (3 collaborations)
• Torsten Partsch of San Jose CA (US) (1 collaborations)
• Michael Alexander Hamburg (1 collaborations)
• John Eric Linstadt of Palo Alto CA (US) (1 collaborations)
• Evan Lawrence Erickson of Chapel Hill NC (US) (1 collaborations)
• James E. Harris of Tyler TX (US) (1 collaborations)
• Ian P. Shaeffer of Los Gatos CA (US) (1 collaborations)
• Michael Raymond Miller of Raleigh NC (US) (1 collaborations)
• Collins Williams of Raleigh NC (US) (1 collaborations)