18658740. Memory Calibration and Margin Check simplified abstract (Apple Inc.)
Contents
Memory Calibration and Margin Check
Organization Name
Inventor(s)
Robert E. Jeter of Santa Clara CA (US)
Jingkui Zheng of Santa Clara CA (US)
Ritesh J. Shah of Sunnyvale CA (US)
Veera Chockalingam of Santa Clara CA (US)
Naveen Kumar Korada of Round Rock TX (US)
Memory Calibration and Margin Check - A simplified explanation of the abstract
This abstract first appeared for US patent application 18658740 titled 'Memory Calibration and Margin Check
Simplified Explanation: The patent application describes a memory calibration method that includes a margin check to optimize memory performance without the need for repeated horizontal calibrations.
Key Features and Innovation:
- Memory controller performs horizontal memory calibrations during initialization for different performance states.
- Information on differences between calibration results for various performance states is stored.
- When transitioning between performance states, memory parameters are adjusted based on stored differences.
- Eliminates the need for repeated horizontal calibrations, improving efficiency and performance.
Potential Applications: This technology can be applied in various memory subsystems, such as computer systems, servers, and other devices requiring optimized memory performance.
Problems Solved: The technology addresses the issue of time-consuming and repetitive memory calibrations by utilizing stored calibration differences to adjust memory parameters efficiently.
Benefits:
- Improved memory performance without the need for repeated calibrations.
- Enhanced efficiency in memory subsystems.
- Streamlined transition between different performance states.
Commercial Applications: Optimizing memory performance in computer systems, servers, and other devices can lead to improved overall system efficiency and performance, making this technology valuable in the tech industry.
Questions about Memory Calibration with a Margin Check: 1. How does the margin check in memory calibration improve overall system performance? 2. What are the potential cost-saving benefits of implementing this memory calibration method?
Frequently Updated Research: Stay updated on advancements in memory calibration technologies and their impact on overall system performance to ensure optimal memory subsystem efficiency.
Original Abstract Submitted
Memory calibration with a margin check is disclosed. A memory subsystem includes a memory and a memory controller coupled to the memory. The memory controller includes a calibration circuit configured to perform, during an initialization process, horizontal memory calibrations for ones of a plurality of performance states and to determine and store, in a storage circuit, information indicative of a set of differences between calibration results for pairs of the plurality of performance states. The memory controller is further configured to, subsequent to the initialization process and in response to a change from a first one of the plurality of performance states to a second one of the plurality of performance states set initial memory parameters for the second performance state based on the set of differences. Thereafter, operation begins in the second performance state without performing an initial horizontal calibration.
