18651321. INTEGRATED CIRCUIT PACKAGES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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INTEGRATED CIRCUIT PACKAGES

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chung-Shi Liu of Hsinchu (TW)

Jiun Yi Wu of Zhongli City (TW)

Chien-Hsun Lee of Chu-tung Town (TW)

INTEGRATED CIRCUIT PACKAGES - A simplified explanation of the abstract

This abstract first appeared for US patent application 18651321 titled 'INTEGRATED CIRCUIT PACKAGES

The abstract describes a device with an integrated circuit die encapsulated by an encapsulant, a conductive via extending through the encapsulant, and a redistribution structure on the encapsulant.

  • The redistribution structure includes a metallization pattern electrically coupled to the integrated circuit die and the conductive via, a dielectric layer with a specific thickness, and a first under-bump metallurgy (UBM) physically and electrically coupled to the metallization pattern.
  • The first UBM has a via portion and a bump portion, with a specific width-to-thickness ratio.

Potential Applications:

  • This technology can be used in semiconductor packaging and microelectronics industries for advanced integrated circuit designs.
  • It can improve the performance and reliability of electronic devices by enhancing signal transmission and power distribution.

Problems Solved:

  • Enhances electrical connectivity and signal integrity in integrated circuits.
  • Provides a reliable and efficient method for packaging and interconnecting semiconductor components.

Benefits:

  • Improved electrical performance and signal transmission.
  • Enhanced reliability and durability of electronic devices.
  • Cost-effective and efficient packaging solution for integrated circuits.

Commercial Applications:

  • This technology can be applied in the development of high-performance electronic devices such as smartphones, computers, and automotive electronics.
  • It can also be used in the aerospace and defense industries for advanced electronic systems.

Questions about the Technology: 1. How does the specific thickness of the dielectric layer impact the performance of the device? 2. What are the advantages of using a conductive via in the encapsulation of the integrated circuit die?


Original Abstract Submitted

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 μm to 30 μm; and a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first UBM being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66.

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