18628881. MEMORY CONTROL APPARATUS AND MEMORY CONTROL METHOD simplified abstract (CANON KABUSHIKI KAISHA)
Contents
MEMORY CONTROL APPARATUS AND MEMORY CONTROL METHOD
Organization Name
Inventor(s)
DAISUKE Shiraishi of Tokyo (JP)
MEMORY CONTROL APPARATUS AND MEMORY CONTROL METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 18628881 titled 'MEMORY CONTROL APPARATUS AND MEMORY CONTROL METHOD
The patent application describes a memory control apparatus for a DRAM with multiple banks.
- First generation unit generates access commands in response to access requests and stores them in a buffer.
- Second generation unit generates refresh requests for specific banks in the DRAM.
- Issuance unit issues DRAM commands based on the access commands in the buffer and refresh requests.
- The second generation unit determines the target bank for refresh requests based on dependencies and access targets.
Potential Applications: - Memory management systems - Data processing applications - Computer hardware design
Problems Solved: - Efficient memory access control - Improved DRAM performance - Enhanced data processing capabilities
Benefits: - Optimal memory utilization - Faster data access speeds - Reduced latency in memory operations
Commercial Applications: - Semiconductor industry - Computer manufacturing - Data center infrastructure
Questions about Memory Control Apparatus: 1. How does the memory control apparatus improve DRAM performance? 2. What are the key differences between the first and second generation units in the apparatus?
Frequently Updated Research: - Ongoing studies on memory access optimization techniques - Research on advanced DRAM architectures and designs
By focusing on optimizing memory access and improving DRAM performance, the memory control apparatus described in the patent application has the potential to revolutionize data processing systems and enhance overall computing efficiency.
Original Abstract Submitted
A memory control apparatus that controls access to a DRAM including a plurality of banks, the apparatus comprising: a first generation unit that generates an access command in response to an access request to the DRAM, and store the access command in a buffer; a second generation unit that generates a refresh request specifying a bank to the DRAM; and an issuance unit that issues a DRAM command to the DRAM, based on the access command stored in the buffer and the refresh request generated by the second generation unit, wherein the second generation unit determines a target bank of the refresh request from among banks remaining after excluding, from the plurality of banks, a bank that is an access target of the access command stored in the buffer and having a dependency relationship that needs to maintain issuance order.
