18627993. THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP STRUCTURES FOR WORD LINE CONTACTS AND METHODS OF EMPLOYING THE SAME simplified abstract (SanDisk Technologies LLC)
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP STRUCTURES FOR WORD LINE CONTACTS AND METHODS OF EMPLOYING THE SAME
Organization Name
Inventor(s)
Toshiyuki Isome of Yokkaichi (JP)
Hirofumi Tokita of Yokkaichi (JP)
THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP STRUCTURES FOR WORD LINE CONTACTS AND METHODS OF EMPLOYING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18627993 titled 'THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP STRUCTURES FOR WORD LINE CONTACTS AND METHODS OF EMPLOYING THE SAME
The abstract describes a device with alternating insulating and electrically conductive layers in a memory array region and a staircase region, with stepped surfaces in the staircase region.
- The device includes vertical stacks of insulating and spacer material plates on stepped surfaces in the staircase region.
- A dielectric material portion with a stepped bottom surface contacts each vertical stack.
- Layer contact via structures extend through the dielectric material portion and vertical stacks to contact the electrically conductive layers.
Potential Applications: - Memory storage devices - Semiconductor manufacturing - Electronics industry
Problems Solved: - Improved memory array design - Enhanced electrical conductivity - Efficient layer contact structures
Benefits: - Increased memory storage capacity - Enhanced device performance - Improved reliability and durability
Commercial Applications: Title: Advanced Memory Array Device for Semiconductor Industry This technology can be used in the production of high-performance memory storage devices, catering to the growing demand in the semiconductor industry.
Questions about the technology: 1. How does this device improve memory storage capacity compared to traditional designs? 2. What are the specific benefits of using vertical stacks in the staircase region for layer contact structures?
Original Abstract Submitted
A device includes an alternating stack of insulating layers and electrically conductive layers extending along a first horizontal direction through a first memory array region and a staircase region, where the alternating stack comprises stepped surfaces in the staircase region, vertical stacks of at least one insulating plate and at least one spacer material plate, where each of the vertical stacks is located on a respective horizontal surface segment of the stepped surfaces in the staircase region, a dielectric material portion located in the staircase region having a stepped bottom surface and contacting each of the vertical stacks, and layer contact via structures located in the staircase region and vertically extending through the dielectric material portion and a respective vertical stack of the vertical stacks and contacting a respective one of the electrically conductive layers.
