18626135. DYNAMIC PARITY SCHEME simplified abstract (Micron Technology, Inc.)
Contents
- 1 DYNAMIC PARITY SCHEME
- 1.1 Organization Name
- 1.2 Inventor(s)
- 1.3 DYNAMIC PARITY SCHEME - A simplified explanation of the abstract
- 1.4 Simplified Explanation
- 1.5 Key Features and Innovation
- 1.6 Potential Applications
- 1.7 Problems Solved
- 1.8 Benefits
- 1.9 Commercial Applications
- 1.10 Prior Art
- 1.11 Frequently Updated Research
- 1.12 Questions about Dynamic Parity Scheme
- 1.13 Original Abstract Submitted
DYNAMIC PARITY SCHEME
Organization Name
Inventor(s)
Gennaro Schettino of Casamicciola Terme (NA) (IT)
Luca Porzio of Casalnuovo (NA) (IT)
DYNAMIC PARITY SCHEME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18626135 titled 'DYNAMIC PARITY SCHEME
Simplified Explanation
The patent application describes methods, systems, and devices for a dynamic parity scheme in a memory system. This system includes memory blocks with pages of memory cells storing data and parity information. The quantity of pages storing parity information can be increased to enhance data reliability based on certain conditions.
Key Features and Innovation
- Memory system with dynamic parity scheme
- Memory blocks with pages storing data and parity information
- Increase in quantity of pages storing parity information to improve data reliability
- Trigger for increasing pages based on access operations or error detection
Potential Applications
The technology can be applied in various memory systems, data storage devices, and computer systems where data reliability is crucial. It can enhance the integrity of stored data and prevent data loss due to errors.
Problems Solved
The technology addresses the issue of data reliability in memory systems by dynamically adjusting the quantity of pages storing parity information. This helps in improving the overall reliability of the stored data.
Benefits
- Enhanced data reliability
- Improved data integrity
- Prevention of data loss due to errors
- Increased system performance
Commercial Applications
The dynamic parity scheme can be utilized in data centers, servers, cloud storage systems, and other storage devices where data integrity is a critical factor. It can be marketed as a solution to enhance data reliability and prevent data loss.
Prior Art
Readers can explore prior patents related to memory systems, data storage devices, and error correction techniques to understand the evolution of dynamic parity schemes in the industry.
Frequently Updated Research
Researchers are constantly exploring new methods to enhance data reliability and error correction in memory systems. Stay updated on the latest advancements in dynamic parity schemes for memory devices.
Questions about Dynamic Parity Scheme
How does the dynamic parity scheme improve data reliability in memory systems?
The dynamic parity scheme increases the quantity of pages storing parity information based on specific conditions, which helps in enhancing data reliability by improving error detection and correction capabilities.
What are the potential applications of the dynamic parity scheme in commercial settings?
The dynamic parity scheme can be applied in data centers, servers, and storage devices to ensure data integrity, prevent data loss, and enhance system performance.
Original Abstract Submitted
Methods, systems, and devices for a dynamic parity scheme are described. A memory system may include a memory device with multiple blocks of memory cells, where each block includes a first quantity of pages of memory cells storing data and a second quantity of pages of memory cells storing parity information associated with the data. In some cases, the memory system may increase the quantity of pages in a block of memory cells storing parity information to improve a reliability of the data stored in the block of memory cells. For example, the memory system may increase the quantity of pages storing parity information at the block of memory cells after performing a threshold quantity of access operations at the block of memory cells or in response to detecting more than a threshold quantity of errors in data stored at the block of memory cells.
