18608191. Pitch Reduction Technology Using Alternating Spacer Depositions During the Formation of a Semiconductor Device and Systems Including Same simplified abstract (Lodestar Licensing Group LLC)

Pitch Reduction Technology Using Alternating Spacer Depositions During the Formation of a Semiconductor Device and Systems Including Same

Organization Name

Lodestar Licensing Group LLC

Inventor(s)

Baosuo Zhou of Boise ID (US)

Mirzafer K. Abatchev of Fremont CA (US)

Ardavan Niroomand of Boise ID (US)

Paul A. Morgan of Kuna ID (US)

Shuang Meng of Austin TX (US)

Joseph Neil Greeley of Boise ID (US)

Brian J. Coppa of Tempe AZ (US)

Pitch Reduction Technology Using Alternating Spacer Depositions During the Formation of a Semiconductor Device and Systems Including Same - A simplified explanation of the abstract

This abstract first appeared for US patent application 18608191 titled 'Pitch Reduction Technology Using Alternating Spacer Depositions During the Formation of a Semiconductor Device and Systems Including Same

Simplified Explanation: The patent application describes a method for increasing the density of features on a layer using self-aligned spacers.

• An initial sacrificial patterning layer is formed over the layer to be etched.
• Spacer layers are formed and etched to increase feature density.
• The number and dimensions of spacer layers depend on the desired density increase.

Key Features and Innovation:

• Utilizes self-aligned spacers to increase feature density.
• Allows for precise control over feature density.
• Can be applied in semiconductor device manufacturing.

Potential Applications:

• Semiconductor manufacturing
• Nanotechnology
• Microelectronics

Problems Solved:

• Increasing feature density on a layer
• Achieving precise control over feature dimensions

Benefits:

• Improved resolution and precision in feature patterning
• Enhanced performance of semiconductor devices
• Cost-effective method for increasing feature density

Commercial Applications:

• Semiconductor industry for advanced device manufacturing
• Nanotechnology companies for precise feature patterning

Prior Art: Prior art related to this technology can be found in the field of semiconductor manufacturing processes, specifically in methods for increasing feature density on layers.

Frequently Updated Research: Research on advanced lithography techniques and semiconductor manufacturing processes may provide further insights into improving feature density using self-aligned spacers.

Questions about the Technology: 1. How does the use of self-aligned spacers improve feature density on a layer? 2. What are the potential challenges in implementing this method in semiconductor manufacturing processes?

Original Abstract Submitted

A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.