18604940. MEMORY SYSTEM simplified abstract (Kioxia Corporation)
Contents
MEMORY SYSTEM
Organization Name
Inventor(s)
Masanobu Shirakawa of Chigasaki (JP)
MEMORY SYSTEM - A simplified explanation of the abstract
This abstract first appeared for US patent application 18604940 titled 'MEMORY SYSTEM
The memory system described in the abstract includes a memory and a memory controller with an encoder that generates codewords from data sections for error correction.
- The encoder creates a first codeword with error correction code parity based on the rank of the data sections.
- The first codeword consists of bit strings associated with columns and rows, which are then written into magnetic bodies by the memory controller.
- Each magnetic body stores a different bit string, ensuring data integrity.
Key Features and Innovation:
- Error correction through codewords based on data section rank.
- Storage of bit strings in magnetic bodies for data integrity.
Potential Applications:
- Data storage systems requiring error correction.
- High-performance computing applications.
- Security systems where data integrity is crucial.
Problems Solved:
- Ensures data integrity through error correction.
- Optimizes memory storage and retrieval processes.
Benefits:
- Improved data reliability.
- Enhanced system performance.
- Reduced risk of data loss.
Commercial Applications:
- Data centers.
- Cloud computing services.
- High-speed data processing industries.
Questions about Memory Systems: 1. How does the memory controller ensure data integrity through error correction? 2. What are the potential applications of this memory system technology?
Frequently Updated Research: Ongoing research focuses on enhancing error correction algorithms for even greater data reliability and integrity.
Original Abstract Submitted
A memory system includes a memory and a memory controller. The memory controller includes an encoder including a first encoder configured to generate a first codeword from a plurality of first data sections. The first codeword includes a first error correction code parity for correcting errors in number based on a rank in the plurality of first data sections and the first codeword. The first codeword includes a plurality of first bit strings respectively associated with a plurality of columns. The first bit strings each include a plurality of bits respectively associated with a plurality of rows. The memory controller is configured to write the plurality of first bit strings into the plurality of magnetic bodies, respectively, such that the magnetic body in which one of the first bit strings is written is different.
