18603281. MEMORY DEVICE simplified abstract (Kioxia Corporation)
Contents
MEMORY DEVICE
Organization Name
Inventor(s)
Ryu Ogiwara of Yokohama Kanagawa (JP)
Hidehiro Shiga of Yokohama Kanagawa (JP)
Daisaburo Takashima of Yokohama Kanagawa (JP)
MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18603281 titled 'MEMORY DEVICE
The abstract of this patent application describes a device with a memory cell and a sense amplification circuit that reads data from the memory cell based on voltage comparisons.
- Memory cell stores first data with first, second, and third bits
- Sense amplification circuit compares bit line voltage to first and second reference voltages
- Reads first data based on results of voltage comparisons
- Retains second data with a first code if bit line voltage is equal to or lower than first reference voltage during a first period
- Retains first data after the first period
Potential Applications: - Memory storage devices - Data processing systems - Integrated circuits
Problems Solved: - Efficient data reading from memory cells - Accurate voltage comparisons for data retrieval
Benefits: - Improved data storage and retrieval efficiency - Enhanced performance of memory devices - Increased reliability of data processing systems
Commercial Applications: Title: Advanced Memory Storage Technology for Enhanced Data Processing This technology can be utilized in various commercial applications such as: - Consumer electronics - Data centers - Communication systems
Questions about the technology: 1. How does the sense amplification circuit improve data reading efficiency? 2. What are the potential implications of using multiple reference voltages in memory devices?
Original Abstract Submitted
According to one embodiment, a device includes: a memory cell coupled to a bit line and configured to store first data including first, second, and third bits; and a sense amplification circuit configured to perform a first comparison between a bit line voltage and a first reference voltage, and a second comparison between the bit line voltage and a second reference voltage lower than the first reference voltage, and to read the first data from the memory cell based on results of the first and second comparisons. The sense amplification circuit is configured to retain second data having a first code in response to the bit line voltage becoming equal to or lower than the first reference voltage during a first period from a start of operation to a first time point, and retain the first data after the first period.
