18597150. SEMICONDUCTOR MEMORY DEVICE simplified abstract (Kioxia Corporation)
Contents
SEMICONDUCTOR MEMORY DEVICE
Organization Name
Inventor(s)
Hiroyuki Yamasaki of Nagoya Aichi (JP)
Masayoshi Tagami of Kuwana Mie (JP)
Katsuaki Isobe of Yokohama Kanagawa (JP)
SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18597150 titled 'SEMICONDUCTOR MEMORY DEVICE
The abstract describes a semiconductor memory device with two chips, each containing stacked bodies, semiconductor films, contact plugs, and planar wiring lines.
- The contact plug extends between the stacked bodies in a specific direction.
- The planar wiring line covers the contact plug and is connected to it, extending in multiple directions.
- The first chip is positioned opposite the second chip with respect to the first stacked body, contact plug, and second stacked body.
Potential Applications: - This technology can be used in various semiconductor memory devices to improve performance and efficiency.
Problems Solved: - Enhances the connectivity and data transfer capabilities within the semiconductor memory device. - Optimizes the layout and design of the memory device for better functionality.
Benefits: - Increased speed and reliability in data storage and retrieval processes. - Enhanced overall performance of semiconductor memory devices.
Commercial Applications: - This innovation can be applied in the manufacturing of advanced memory modules for computers, smartphones, and other electronic devices.
Questions about the Technology: 1. How does the positioning of the first chip opposite the second chip impact the overall functionality of the semiconductor memory device? 2. What are the specific advantages of using planar wiring lines in this memory device design?
Frequently Updated Research: - Stay updated on the latest advancements in semiconductor memory technology to incorporate new features and improvements into future iterations of this device.
Original Abstract Submitted
According to one embodiment, in a semiconductor memory device including a first chip and a second chip. The first chip includes a first stacked body, a first semiconductor film, a second stacked body, a second semiconductor film, a contact plug and a first planar wiring line. The contact plug extends in the third direction between the first stacked body and the second stacked body. The first planar wiring line is disposed on a side opposite to the second chip with respect to the first stacked body, the contact plug, and the second stacked body, the first planar wiring line extending in the first direction and the second direction, covering at least the contact plug, and being connected to the contact plug.
