18594066. MEMORY DEVICE simplified abstract (Kioxia Corporation)
Contents
MEMORY DEVICE
Organization Name
Inventor(s)
Manabu Sato of Chigasaki Kanagawa (JP)
MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18594066 titled 'MEMORY DEVICE
Simplified Explanation:
The memory device described in the patent application consists of a memory cell array with a block containing two transistors and multiple memory cells connected in series. A row control circuit manages the state of the block based on an address decoding result and stores information about the block's defect status. It can independently control the electrical state of the second select gate line.
- The memory device includes a unique structure with transistors, memory cells, and a row control circuit.
- The row control circuit can set the block to a selected or unselected state based on address decoding results.
- Information about the block's defect status is stored within the memory device.
- The second select gate line can be controlled independently of the first select gate line by the row control circuit.
Key Features and Innovation:
- Memory cell array with a block structure containing transistors and memory cells.
- Row control circuit for managing block state based on address decoding.
- Storage of information indicating block defect status.
- Independent control of the second select gate line by the row control circuit.
Potential Applications:
- Data storage devices
- Embedded systems
- Consumer electronics
Problems Solved:
- Efficient memory management
- Enhanced defect detection and handling
- Improved control over memory cell array
Benefits:
- Increased reliability in memory operations
- Better utilization of memory resources
- Enhanced performance in data storage applications
Commercial Applications:
The technology described in the patent application could have significant implications in the development of advanced memory devices for various industries, including data storage, embedded systems, and consumer electronics. By offering improved memory management, defect detection, and control features, this innovation could lead to more reliable and efficient memory solutions in the market.
Questions about Memory Devices: 1. How does the row control circuit in the memory device manage the block's state based on address decoding? 2. What are the potential applications of this memory device technology in different industries?
Original Abstract Submitted
A memory device includes a memory cell array including a block including a first transistor connected to a first select gate line, a second transistor connected to a second select gate line, and a plurality of memory cells connected in series between the first and second transistors and each connected to one corresponding word line of a plurality of word lines, and a row control circuit that outputs a control signal for setting the block to be in a selected state or an unselected state based on a result of decoding an address, stores information indicating whether the block is a non-defective block, and controls an electrical state of the second select gate line independently of the first select gate line based on the control signal and the information.
