18593980. SEMICONDUCTOR MEMORY DEVICE simplified abstract (Kioxia Corporation)
Contents
SEMICONDUCTOR MEMORY DEVICE
Organization Name
Inventor(s)
Yoichi Minemura of Yokkaichi Mie (JP)
SEMICONDUCTOR MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18593980 titled 'SEMICONDUCTOR MEMORY DEVICE
Simplified Explanation: The patent application describes a semiconductor memory device with stacked conductive layers and insulating layers, a semiconductor film for memory cell transistors, an insulating film, and a control circuit for write operations.
- Stacked body with conductive and insulating layers
- Semiconductor film for memory cell transistors
- Insulating film between conductive layers and semiconductor film
- Control circuit for write operations
- Varying transfer voltage based on number of bits being written
Potential Applications: This technology can be used in various memory storage devices such as solid-state drives, smartphones, tablets, and other electronic devices requiring non-volatile memory.
Problems Solved: This technology addresses the need for efficient and reliable write operations in semiconductor memory devices, optimizing the transfer voltage based on the number of bits being written.
Benefits: - Improved write operation efficiency - Enhanced reliability in memory storage - Optimal transfer voltage control
Commercial Applications: The technology can be applied in the development of faster and more reliable memory storage devices, catering to the increasing demand for high-performance electronic gadgets in the consumer market.
Questions about Semiconductor Memory Devices: 1. How does the control circuit optimize the transfer voltage for write operations? 2. What are the potential challenges in implementing this technology in mass-produced memory devices?
Original Abstract Submitted
A semiconductor memory device includes a stacked body in which conductive layers are stacked with an insulating layer interposed therebetween, a semiconductor film to provide a channel for a plurality of memory cell transistors having gates electrically connected to the conductive layers of the stacked body, respectively, an insulating film extending in the stacking direction between the conductive layers and the semiconductor film, and a control circuit configured to control a program voltage to be applied to a conductive layer electrically connected to a memory cell transistor that is a target of a write operation, and a transfer voltage to be applied to conductive layers electrically connected to other memory cell transistors that are not the target of the write operation, wherein the control circuit is configured to vary the transfer voltage to be applied depending on a number of bits that are being written in the write operation.
