18541596. Hardware Mapping simplified abstract (Imagination Technologies Limited)
Contents
Hardware Mapping
Organization Name
Imagination Technologies Limited
Inventor(s)
William Thomas of Hertfordshire (GB)
Ahmed Elkhidir of Hertfordshire (GB)
Hardware Mapping - A simplified explanation of the abstract
This abstract first appeared for US patent application 18541596 titled 'Hardware Mapping
The abstract describes a method of mapping a program to a hardware arrangement with interconnected hardware stages. The hardware stages are analyzed to generate program-independent hardware descriptions for each stage, defining the operation, inputs, and outputs.
- Program-independent hardware descriptions are used to map groups of adjacent program primitive operations to groups of interconnected hardware stages.
- Non-overlapping mappings are generated based on the analysis of the program and hardware arrangement.
- The groups of adjacent program primitive operations are scheduled for execution in a specific order.
Potential Applications: - This technology can be applied in the design and optimization of hardware accelerators for various computing tasks. - It can be used in the development of specialized hardware for specific applications such as image processing, machine learning, and signal processing.
Problems Solved: - Efficient mapping of programs to hardware arrangements. - Optimizing the execution of program operations on hardware stages. - Streamlining the design process of hardware accelerators.
Benefits: - Improved performance and efficiency in executing programs on hardware. - Reduction in development time and cost for designing specialized hardware. - Enhanced flexibility in customizing hardware configurations for specific applications.
Commercial Applications: Title: Hardware Accelerator Design Optimization for Enhanced Performance This technology can be utilized by semiconductor companies, research institutions, and technology firms to develop specialized hardware accelerators for a wide range of applications. The optimized mapping of programs to hardware stages can lead to significant performance improvements and cost savings in the development of custom hardware solutions.
Questions about Hardware Accelerator Design Optimization: 1. How does this technology improve the efficiency of mapping programs to hardware stages? - The technology analyzes the hardware arrangement to generate program-independent hardware descriptions, which are then used to map program operations to hardware stages efficiently. 2. What are the potential applications of this technology in the field of hardware acceleration? - This technology can be applied in various domains such as image processing, machine learning, and signal processing to optimize the design and performance of hardware accelerators.
Original Abstract Submitted
A method of mapping a program to a hardware arrangement comprising a plurality of interconnected hardware stages. The plurality of hardware stages in the hardware arrangement is analysed to generate, for each stage, a program-independent hardware description defining an operation performed by the stage and inputs and outputs of the stage. The program-independent hardware descriptions are then used when analysing the program to generate a non-overlapping set of mappings between groups of adjacent program primitive operations in the program and groups of interconnected hardware stages in the hardware arrangement. Having generated the non-overlapping set of mappings, the groups of adjacent program primitive operations are scheduled into an order for execution.
