18509250. MEMORY DEVICE simplified abstract (Samsung Electronics Co., Ltd.)
Contents
MEMORY DEVICE
Organization Name
Inventor(s)
Eunhyang Park of Suwon-si (KR)
MEMORY DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18509250 titled 'MEMORY DEVICE
Simplified Explanation: The patent application describes a memory device with a unique configuration in which different read voltages are applied to wordlines and the responses of page buffers connected to bitlines are monitored.
- The memory device has a cell region with multiple memory cells and a peripheral circuit region with row decoders, wordlines, page buffers, and control logic.
- Row decoders apply various read voltages to selected wordlines sequentially.
- Page buffers, each connected to a bitline, monitor the voltage changes on sensing nodes while read voltages are applied to wordlines.
Key Features and Innovation:
- Sequential application of different read voltages to wordlines.
- Monitoring voltage changes on sensing nodes in page buffers.
- Unique configuration of memory cells and peripheral circuitry.
Potential Applications:
- Data storage in electronic devices.
- Embedded memory in microcontrollers.
- Cache memory in computer systems.
Problems Solved:
- Efficient reading of data from memory cells.
- Improved control of memory access.
- Enhanced data retrieval speed.
Benefits:
- Faster data access.
- Higher memory efficiency.
- Enhanced overall system performance.
Commercial Applications: The technology can be utilized in various electronic devices, microcontrollers, and computer systems to improve data storage and retrieval processes, leading to faster and more efficient performance.
Prior Art: Readers can explore prior patents related to memory devices, row decoders, and page buffers to understand the evolution of this technology.
Frequently Updated Research: Stay updated on advancements in memory device technology, particularly in the areas of read voltage application and sensing node monitoring for improved data access.
Questions about Memory Device Technology: 1. How does the unique configuration of the memory device improve data retrieval speed? 2. What are the potential challenges in implementing this technology in different electronic devices?
Original Abstract Submitted
A memory device includes a cell region in which a plurality of memory cells are arranged and a peripheral circuit region in which a row decoder is connected to the plurality of memory cells through a plurality of wordlines, a plurality of page buffers connected to the plurality of memory cells through a plurality of bitlines, and a control logic controlling the row decoder and the plurality of page buffers are arranged. The row decoder inputs a plurality of read voltages having different levels to a selected wordline among the plurality of wordlines in sequence. Each of the plurality of page buffers includes a sensing node connected to one of the plurality of bitlines. Voltages of the sensing nodes included in the page buffers of a portion of the plurality of page buffers decrease differently while each of the plurality of read voltages is input to the selected wordline.
