18404255. DISPLAY APPARATUS simplified abstract (Samsung Display Co., Ltd.)
Contents
DISPLAY APPARATUS
Organization Name
Inventor(s)
Chulkyu Kang of Yongin-si (KR)
DISPLAY APPARATUS - A simplified explanation of the abstract
This abstract first appeared for US patent application 18404255 titled 'DISPLAY APPARATUS
Simplified Explanation: The patent application describes a display apparatus where each pixel consists of multiple components connected in a specific configuration.
Key Features and Innovation:
- Each pixel includes a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor.
- The components are interconnected to control the display of each pixel effectively.
- The first electrode of the second capacitor and the first voltage line are on the same layer, optimizing space and efficiency.
Potential Applications: This technology can be used in various display devices such as televisions, monitors, and mobile screens.
Problems Solved: The technology addresses the need for efficient and compact pixel structures in display devices.
Benefits:
- Improved display quality and performance.
- Space-saving design for compact devices.
- Enhanced energy efficiency.
Commercial Applications: Potential commercial applications include consumer electronics, advertising displays, and automotive displays.
Prior Art: Readers can explore prior patents related to display apparatus design and pixel structure to understand the evolution of this technology.
Frequently Updated Research: Stay updated on advancements in display technology, semiconductor materials, and manufacturing processes to enhance the efficiency of display apparatus.
Questions about Display Apparatus Technology: 1. How does the configuration of transistors and capacitors in each pixel impact display quality? 2. What are the potential future developments in display apparatus technology to look out for?
Original Abstract Submitted
Each pixel of a display apparatus includes a first transistor, a second transistor connected to a first gate of the first transistor and a data line, a third transistor connected to the first gate of the first transistor and a first voltage line, a first capacitor including a first electrode connected to the first gate of the first transistor and a second electrode connected to the second terminal of the first transistor, and a second capacitor including a first electrode connected to the first voltage line and a second electrode connected to the second terminal of the first transistor. The first electrode of the second capacitor and the first voltage line are disposed on a same layer.
