18163416. STRUCTURE AND FORMATION METHOD OF PACKAGE WITH INTEGRATED CHIPS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

STRUCTURE AND FORMATION METHOD OF PACKAGE WITH INTEGRATED CHIPS

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chih-Chao Chou of Hsinchu City (TW)

Yi-Hsun Chiu of Zhubei city Hsinchu County (TW)

Shang-Wen Chang of Jhubei city Hsinchu County (TW)

Ching-Wei Tsai of Hsinchu City (TW)

Chih-Hao Wang of Baoshan Township (TW)

STRUCTURE AND FORMATION METHOD OF PACKAGE WITH INTEGRATED CHIPS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18163416 titled 'STRUCTURE AND FORMATION METHOD OF PACKAGE WITH INTEGRATED CHIPS

The abstract of this patent application describes a method for forming a package structure by disposing a first chip structure over a carrier substrate, forming a back-side interconnection structure, and bonding a second chip structure using dielectric-to-dielectric and metal-to-metal bonding.

• The method involves placing a first chip structure with a front-side interconnection structure on a carrier substrate.
• A back-side interconnection structure is formed over the first chip structure, which has a device portion between the two interconnection structures.
• The back-side interconnection structure includes stacked conductive vias.
• A second chip structure is bonded to the first chip structure using dielectric-to-dielectric and metal-to-metal bonding methods.

Potential Applications: - This technology can be applied in the semiconductor industry for advanced packaging solutions. - It can be used in the development of high-performance electronic devices.

Problems Solved: - Provides a method for creating a package structure with improved interconnection capabilities. - Enables the bonding of multiple chip structures in a reliable and efficient manner.

Benefits: - Enhanced interconnection reliability and performance. - Increased flexibility in chip packaging design.

Commercial Applications: Title: Advanced Semiconductor Packaging Technology for Enhanced Interconnection This technology can be utilized by semiconductor companies to develop cutting-edge electronic devices with improved interconnection capabilities, catering to the growing demand for high-performance and reliable products in various industries.

Questions about Advanced Semiconductor Packaging Technology: 1. How does this technology improve interconnection reliability in chip packaging? 2. What are the key advantages of using dielectric-to-dielectric and metal-to-metal bonding in semiconductor packaging?

Original Abstract Submitted

A package structure and a formation method are provided. The method includes disposing a first chip structure over a carrier substrate. The first chip structure has a front-side interconnection structure facing the carrier substrate. The method also includes forming a back-side interconnection structure over the first chip structure. The first chip structure has a device portion between the back-side interconnection structure and the front-side interconnection structure. The back-side interconnection structure has stacked conductive vias. The method further includes bonding a second chip structure to the first chip structure using dielectric-to-dielectric bonding and metal-to-metal bonding.