18145744. ACCELERATING KECCAK ALGORITHMS simplified abstract (Intel Corporation)

ACCELERATING KECCAK ALGORITHMS

Organization Name

Intel Corporation

Inventor(s)

Santosh Ghosh of Hillsboro OR (US)

Christoph Dobraunig of St. Veit an der Glan (AT)

Manoj Sastry of Portland OR (US)

Andrew H. Reinders of Portland OR (US)

Regev Shemy of Kiryat Ata (IL)

Qian Wang of Portland OR (US)

Rotem Ohana Peretz of Kfar Zeitim Lower Galili (IL)

Wing Shek Wong of Austin TX (US)

Wajdi Feghali of Boston MA (US)

ACCELERATING KECCAK ALGORITHMS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18145744 titled 'ACCELERATING KECCAK ALGORITHMS

The method described in the abstract involves fetching an encoded parity instruction, decoding it, and executing it to perform an XOR operation and store the result in a register.

• Fetching an encoded parity instruction with opcodes and source/destination identifiers
• Decoding the instruction to generate a decoded parity instruction
• Executing the decoded instruction to retrieve operands, perform an XOR operation, and store the result

Potential Applications: - Data processing systems - Error detection and correction mechanisms - Cryptographic applications

Problems Solved: - Efficient processing of data - Parity generation for error detection - Secure data encryption

Benefits: - Improved data processing speed - Enhanced error detection capabilities - Secure data encryption methods

Commercial Applications: Title: "Advanced Data Processing Technology for Enhanced Security" This technology can be used in industries such as cybersecurity, data centers, and telecommunications for secure and efficient data processing.

Questions about the technology: 1. How does this technology improve data processing efficiency? - This technology streamlines the process of generating parity values for error detection, leading to faster data processing. 2. What are the potential security implications of using this technology? - By performing XOR operations and storing parity values, this technology enhances data security and encryption methods.

Original Abstract Submitted

A method comprises fetching, by fetch circuitry, an encoded parity instruction comprising at least one opcode, a first source identifier for a first source, a second source identifier for a second source, a third source identifier for a third source, and a destination identifier for a destination, decoding, by decode circuitry, the encoded parity instruction to generate a decoded parity instruction; and executing, by execution circuitry, the decoded parity instruction to retrieve operands representing a first register from the first source, a second register from the second source, a third register from the third source, and an index from the third source, perform an XOR operation of four words of data from the first register and single word of data from the second register in a position represented by the index to generate a parity value, and store the parity value in a the first register in a position represented by the index.