18049454. COMMAND ADDRESS FAULT DETECTION USING A PARITY PIN simplified abstract (Micron Technology, Inc.)
Contents
COMMAND ADDRESS FAULT DETECTION USING A PARITY PIN
Organization Name
Inventor(s)
Melissa I. Uribe of El Dorado Hills CA (US)
Aaron P. Boehm of Boise ID (US)
Scott E. Schaefer of Boise ID (US)
Steffen Buch of Taufkirchen (DE)
COMMAND ADDRESS FAULT DETECTION USING A PARITY PIN - A simplified explanation of the abstract
This abstract first appeared for US patent application 18049454 titled 'COMMAND ADDRESS FAULT DETECTION USING A PARITY PIN
The patent application describes a method for command address fault detection using a parity bit in a memory device.
- Memory device receives a set of command address bits and a first parity bit from a host device during a unit interval.
- Memory device generates a second parity bit based on the command address bits and a parity generation process.
- Memory device compares the first and second parity bits to detect faults in the command address.
- An alert signal is transmitted to the host device based on the result of the comparison.
Potential Applications: - Data storage systems - Computer memory modules - Embedded systems
Problems Solved: - Detecting faults in command addresses - Improving data integrity in memory devices
Benefits: - Enhanced reliability of memory systems - Early detection of errors - Improved system performance
Commercial Applications: Title: "Enhanced Memory Error Detection Technology for Data Storage Systems" This technology can be used in data centers, server farms, and other high-performance computing environments to ensure data integrity and system reliability.
Prior Art: There are existing methods for error detection in memory systems, but this patent application introduces a novel approach using parity bits for command address fault detection.
Frequently Updated Research: Research on improving error detection and correction techniques in memory systems is ongoing, with a focus on enhancing data reliability and system performance.
Questions about Command Address Fault Detection using Parity Bit:
Question 1: How does the parity bit help in detecting faults in command addresses? Answer: The parity bit is used to check the integrity of the command address bits by comparing the generated parity bit with the received parity bit.
Question 2: What are the potential implications of this technology in improving data storage systems? Answer: This technology can significantly enhance the reliability and performance of data storage systems by detecting and correcting errors in command addresses, ensuring data integrity.
Original Abstract Submitted
Implementations described herein relate to command address fault detection using a parity bit. A memory device may receive, from a host device via a command address (CA) bus and during a unit interval, a set of CA bits associated with a CA word. The memory device may receive, from the host device via a parity bus and during the unit interval, a first parity bit that is based on the set of CA bits and a parity generation process. The memory device may generate a second parity bit based on the set of CA bits and the parity generation process. The memory device may compare the first parity bit and the second parity bit. The memory device may selectively transmit an alert signal to the host device based on a result of comparing the first parity bit and the second parity bit.
