17932788. ON-CHIP HYBRID ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING WITH THERMAL MITIGATION simplified abstract (QUALCOMM Incorporated)
ON-CHIP HYBRID ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING WITH THERMAL MITIGATION
Organization Name
Inventor(s)
Ranadeep Dutta of Del Mar CA (US)
Jonghae Kim of San Diego CA (US)
Je-Hsiung Lan of San Diego CA (US)
ON-CHIP HYBRID ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING WITH THERMAL MITIGATION - A simplified explanation of the abstract
This abstract first appeared for US patent application 17932788 titled 'ON-CHIP HYBRID ELECTROMAGNETIC INTERFERENCE (EMI) SHIELDING WITH THERMAL MITIGATION
Simplified Explanation
The abstract describes techniques for on-chip electromagnetic interference (EMI) shielding in integrated circuits. Here is a simplified explanation of the patent application:
- An integrated circuit includes a noise-sensitive device with a first metallization layer on one side, containing conductive routing layers forming an on-chip EMI shield.
- A second metallization layer is on the opposite side of the noise-sensitive device, also containing conductive routing layers forming an on-chip EMI shield.
- Potential Applications
- Electronic devices - Communication systems - Automotive electronics
- Problems Solved
- Minimizing electromagnetic interference - Protecting noise-sensitive devices - Improving overall performance of integrated circuits
- Benefits
- Enhanced reliability of electronic devices - Improved signal integrity - Reduced interference in communication systems
- Potential Commercial Applications
- Optimizing EMI Shielding in Integrated Circuits
- Potential Commercial Applications
- Possible Prior Art
There are existing techniques for EMI shielding in integrated circuits, such as using external shielding materials or coatings to reduce interference. However, the specific on-chip EMI shielding configuration described in this patent application may be a novel approach to address EMI issues within the integrated circuit itself.
- Unanswered Questions
- How does the on-chip EMI shielding impact the overall size and layout of the integrated circuit?
The abstract does not provide details on the impact of the on-chip EMI shielding on the physical dimensions and layout of the integrated circuit.
- Are there any limitations or trade-offs associated with implementing on-chip EMI shielding?
The abstract does not mention any potential limitations or trade-offs that may arise from the implementation of on-chip EMI shielding in integrated circuits.
Original Abstract Submitted
Disclosed are techniques for on-chip electromagnetic interference (EMI) shielding. In an aspect, an integrated circuit includes a noise-sensitive device, a first metallization layer disposed on a first side of the noise-sensitive device, wherein the first metallization layer includes a plurality of conductive routing layers, and wherein conductive routing within the plurality of conductive routing layers is configured as a first side of an on-chip electromagnetic interference (EMI) shield around the first side of the noise-sensitive device, and a second metallization layer disposed on a second side of the noise-sensitive device opposite the first side of the noise-sensitive device, wherein the second metallization layer includes one or more conductive routing layers, and wherein conductive routing within the one or more conductive routing layers is configured as a second side of the on-chip EMI shield around the second side of the noise-sensitive device.