17892252. FILM PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
FILM PACKAGE
Organization Name
Inventor(s)
Sungeun Jo of Hwaseong-si (KR)
Kyungsuk Oh of Seongnam-si (KR)
FILM PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17892252 titled 'FILM PACKAGE
Simplified Explanation
The patent application describes a film package that includes a film substrate with opposing surfaces, wiring patterns, semiconductor chips, a protective layer, and conductive films.
- The film package includes a film substrate with opposing surfaces.
- The film substrate has wiring patterns, including an input pattern, an output pattern, and an interconnection pattern.
- The first semiconductor chip is electrically connected to the input pattern and the interconnection pattern.
- The second semiconductor chip is electrically connected to the interconnection pattern and the output pattern.
- A protective layer covers at least a portion of the wiring patterns on the first surface of the film substrate.
- A first conductive film extends in a second direction on the protective layer.
- A second conductive film on the second surface of the film substrate overlaps the first conductive film in a third direction.
Potential applications of this technology:
- Electronic devices and systems that require compact and efficient packaging.
- Semiconductor devices that require multiple chips to be interconnected.
Problems solved by this technology:
- Provides a compact and efficient packaging solution for electronic devices.
- Enables effective interconnection between multiple semiconductor chips.
Benefits of this technology:
- Reduces the size and weight of electronic devices.
- Improves the performance and reliability of semiconductor devices.
- Simplifies the manufacturing process of electronic devices.
Original Abstract Submitted
A film package, includes: a film substrate having first and second surfaces opposing each other; a plurality of wiring patterns respectively including an input pattern, an output pattern, and an interconnection pattern; a first semiconductor chip electrically connected to the input pattern and the interconnection pattern; a second semiconductor chip electrically connected to the interconnection pattern and the output pattern; a protective layer on the first surface to cover at least a portion of the plurality of wiring patterns; a first conductive film on the protective layer and extending in a second direction; and a second conductive film on the second surface to overlap the first conductive film in a third direction.
