17844815. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Pilsung Choi of Cheonan-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17844815 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The patent application describes a semiconductor package that includes a lower substrate, a semiconductor chip, an upper substrate, and a vertical connection structure.
- The lower substrate has a chip mounting region, an interconnection region, and an outer region, and includes a lower wiring layer.
- A first solder resist pattern is on the lower substrate and exposes bonding regions of the lower wiring layer.
- The semiconductor chip is mounted on the chip mounting region and is electrically connected to the lower wiring layer.
- A second solder resist pattern is on the interconnection and outer regions of the lower substrate and is spaced apart from the semiconductor chip.
- The second solder resist pattern includes openings that are disposed on the first openings of the first solder resist pattern.
- The upper substrate covers the semiconductor chip and includes an upper wiring layer.
- A vertical connection structure is on the interconnection region of the lower substrate and electrically connects the upper and lower wiring layers.
- A solder resist spacer is on the second solder resist pattern on the outer region of the lower substrate.
Potential applications of this technology:
- Semiconductor packaging for electronic devices such as smartphones, tablets, and computers.
- Integrated circuits and microprocessors.
Problems solved by this technology:
- Provides a reliable and efficient way to connect the upper and lower wiring layers in a semiconductor package.
- Protects the bonding regions of the lower wiring layer from damage during the packaging process.
Benefits of this technology:
- Improved electrical connection between the upper and lower wiring layers.
- Enhanced reliability and durability of the semiconductor package.
- Simplified manufacturing process for semiconductor packaging.
Original Abstract Submitted
A semiconductor package includes a lower substrate having a chip mounting region, an interconnection region surrounding the chip mounting region, and an outer region surrounding the interconnection region, and includes a lower wiring layer. A first solder resist pattern has first openings exposing bonding regions of the lower wiring layer. A semiconductor chip is on the chip mounting region and is electrically connected to the lower wiring layer. A second solder resist pattern is on the first solder resist pattern on the interconnection and outer regions and is spaced apart from the semiconductor chip, and includes second openings disposed on the first openings. An upper substrate covers the semiconductor chip, and includes an upper wiring layer. A vertical connection structure is on the interconnection region and electrically connects the upper and lower wiring layers. A solder resist spacer is on the second solder resist pattern on the outer region.
