17831290. PRE-DECODER CIRCUITY simplified abstract (Micron Technology, Inc.)
Contents
PRE-DECODER CIRCUITY
Organization Name
Inventor(s)
Byung S. Moon of Plano TX (US)
Ramachandra Rao Jogu of McKinney TX (US)
PRE-DECODER CIRCUITY - A simplified explanation of the abstract
This abstract first appeared for US patent application 17831290 titled 'PRE-DECODER CIRCUITY
Simplified Explanation
The present disclosure is about pre-decoder circuitry in memory arrays. It describes a configuration where a positive voltage is applied to the first gate and a negative voltage is applied to the second gate of the decoder circuitry for a positive configuration of memory cells. For a negative configuration of memory cells, zero volts is applied to the first gate and a negative voltage is applied to the second gate.
- The patent application describes apparatuses, methods, and systems for pre-decoder circuitry in memory arrays.
- The pre-decoder circuitry includes a memory array with multiple memory cells.
- The decoder circuitry is connected to the memory array and consists of two n-type transistors with separate gates.
- The pre-decoder circuitry is designed to provide a bias condition for the gates of the transistors to generate a selection signal for one of the memory cells.
- The bias condition involves applying a positive voltage to the first gate and a negative voltage to the second gate for a positive configuration of memory cells.
- For a negative configuration of memory cells, the bias condition involves applying zero volts to the first gate and a negative voltage to the second gate.
Potential Applications
- Memory arrays in electronic devices
- Data storage systems
- Computer processors
Problems Solved
- Efficient selection of memory cells in a memory array
- Simplified circuitry design for memory decoding
Benefits
- Improved performance and reliability of memory arrays
- Reduced power consumption
- Simplified circuitry design
Original Abstract Submitted
The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate, and pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises: a positive voltage for the first gate and a negative voltage for the second gate for a positive configuration for the memory cells, and zero volts for the first gate and the negative voltage for the second gate for a negative configuration for the memory cells.
