17823450. Dynamic Address Scramble simplified abstract (Micron Technology, Inc.)
Contents
Dynamic Address Scramble
Organization Name
Inventor(s)
Erik T. Barmon of Boise ID (US)
Nathaniel J. Meier of Boise ID (US)
Kang-Yong Kim of Boise ID (US)
Dynamic Address Scramble - A simplified explanation of the abstract
This abstract first appeared for US patent application 17823450 titled 'Dynamic Address Scramble
Simplified Explanation
The patent application describes apparatuses and methods for loading different address scramble patterns on memory devices, which can help prevent malicious actors from discovering the layout of a particular memory device.
- Memory devices can load different address scramble patterns on memory dies to prevent usage-based disturb attacks.
- Address scramble patterns may include logical-to-physical conversion of rows in the memory device or memory dies.
- The address scrambles can be changed at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable.
- Potential Applications:**
- Memory devices in computer systems
- Data storage devices
- Security systems
- Problems Solved:**
- Preventing malicious actors from discovering the layout of memory devices
- Enhancing security of memory devices
- Protecting data stored on memory devices
- Benefits:**
- Increased security against usage-based disturb attacks
- Enhanced protection for sensitive data
- Improved reliability of memory devices
Original Abstract Submitted
Described apparatuses and methods enable a system including at least one memory device to load different address scramble patterns on dies of the memory device. The address scramble patterns may include the logical-to-physical conversion of rows in the memory device or the memory dies. In aspects, the apparatuses and methods can change the address scrambles at different intervals, such as after a power reset or when the data stored on the memory device is invalid, not current, flushable, or erasable. The described aspects may reduce effectiveness of usage-based disturb attacks used by malicious actors to discover a layout of a type of particular memory device or memory die.
