17806985. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 17806985 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The abstract describes a semiconductor package that includes a substrate, a redistribution layer, a solder resist layer, a conductive terminal, a solder ball, and a semiconductor chip. The redistribution layer has a wiring pad, a recess, a metal seed layer, and a wiring post.
- The semiconductor package includes a substrate with a wiring pattern.
- A redistribution layer is placed on top of the substrate.
- A solder resist layer is placed on top of the redistribution layer and has a recess.
- A conductive terminal is located inside the recess of the solder resist layer.
- A solder ball is placed on the conductive terminal.
- A semiconductor chip is placed on top of the solder resist layer and directly connected to the redistribution layer through the solder ball.
- The redistribution layer includes a wiring pad with a recess.
- A metal seed layer is located inside the recess of the wiring pad.
- A wiring post is partially placed on the metal seed layer inside the recess of the wiring pad.
Potential Applications
- Semiconductor packaging industry
- Electronics manufacturing
Problems Solved
- Simplifies the process of connecting a semiconductor chip to a substrate
- Provides a more efficient and reliable electrical connection
Benefits
- Improved performance and reliability of semiconductor packages
- Simplified manufacturing process
- Enhanced electrical connectivity between components
Original Abstract Submitted
A semiconductor package includes a substrate including a first wiring pattern, a redistribution layer disposed on an upper surface of the substrate, a solder resist layer disposed on an upper surface of the redistribution layer and including a second recess formed inside the solder resist layer, a first conductive terminal disposed on sidewalls and a bottom surface of the second recess, a first solder ball disposed on the first conductive terminal, and a semiconductor chip disposed on the solder resist layer and electrically directly connected to the redistribution layer through the first solder ball. The redistribution layer includes a first wiring pad, a first recess formed on an upper surface of the first wiring pad, a first metal seed layer disposed on sidewalls and a bottom surface of the first recess, and a first wiring post at least partially disposed on the first metal seed layer inside the first recess.
