17680410. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

SEMICONDUCTOR PACKAGE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.

Inventor(s)

YONGHWAN Kwon of Yongin-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 17680410 titled 'SEMICONDUCTOR PACKAGE

Simplified Explanation

The patent application describes a semiconductor package that includes several components such as a semiconductor chip, redistribution pattern, protection layer, conductive pattern, buffer pattern, and under bump pattern.

• The semiconductor package consists of a semiconductor chip, which is the main component.
• A redistribution pattern is present on the bottom surface of the semiconductor chip and is connected to it.
• A protection layer covers the bottom surface of the redistribution pattern, providing a shield.
• A conductive pattern is located on the bottom surface of the protection layer and is connected to the redistribution pattern.
• A buffer pattern is in contact with the bottom surface of a part of the conductive pattern and the bottom surface of the protection layer.
• An under bump pattern is present on the bottom surface of another part of the conductive pattern and covers the bottom surface and side surface of the buffer pattern. It is connected to the second part of the conductive pattern.

Potential applications of this technology:

• Semiconductor packaging industry
• Electronics manufacturing

Problems solved by this technology:

• Provides protection to the semiconductor chip and redistribution pattern.
• Ensures proper connectivity between different components.
• Enhances the overall performance and reliability of the semiconductor package.

Benefits of this technology:

• Improved protection and reliability of the semiconductor chip.
• Enhanced connectivity and performance of the semiconductor package.
• Simplified manufacturing process.

Original Abstract Submitted

Disclosed is a semiconductor package comprising a semiconductor chip, a redistribution pattern on a bottom surface of the semiconductor chip and coupled to the semiconductor chip, a protection layer that covers a bottom surface of the redistribution pattern, a conductive pattern on a bottom surface of the protection layer and coupled to the redistribution pattern, a buffer pattern in contact with a bottom surface of a first part of the conductive pattern and with the bottom surface of the protection layer, and an under bump pattern on a bottom surface of the second part of the conductive pattern and covering a bottom surface and a side surface of the buffer pattern. The under bump pattern is coupled to the second part of the conductive pattern.