18120827. STORAGE SYSTEM simplified abstract (Hitachi, Ltd.)

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STORAGE SYSTEM

Organization Name

Hitachi, Ltd.

Inventor(s)

Kentaro Shimada of Tokyo (JP)

Masanori Takada of Tokyo (JP)

STORAGE SYSTEM - A simplified explanation of the abstract

This abstract first appeared for US patent application 18120827 titled 'STORAGE SYSTEM

The protocol chip facilitates communication between a host apparatus and multiple processors.

  • The protocol chip uses address translation units to route requests and responses between the host apparatus and processors.
  • When the first processor is unable to process a request, the protocol chip directs the request to a second processor.
  • The second processor responds to the request and sends the response back through the protocol chip.
  • This system allows for efficient processing and communication between the host apparatus and multiple processors.

Potential Applications:

  • This technology can be used in multi-processor systems where tasks need to be distributed among different processors.
  • It can be applied in servers, data centers, and other computing systems that require high processing power and efficient communication.

Problems Solved:

  • Efficient distribution of tasks among multiple processors.
  • Seamless communication between the host apparatus and different processors.
  • Improved overall system performance and processing speed.

Benefits:

  • Increased processing power and speed.
  • Enhanced system efficiency and performance.
  • Better utilization of resources in multi-processor systems.

Commercial Applications:

  • This technology can be valuable in industries that rely on high-performance computing systems, such as finance, scientific research, and artificial intelligence development.

Prior Art:

  • Prior research in multi-processor systems and communication protocols may provide insights into similar technologies and approaches.

Frequently Updated Research:

  • Stay updated on advancements in multi-processor systems, communication protocols, and address translation technologies to enhance the efficiency and performance of such systems.

Questions about the technology: 1. How does the protocol chip determine which processor to route a request to?

  The protocol chip decides based on the availability and processing capabilities of the processors.

2. What are the potential challenges in implementing this technology in real-world applications?

  Possible challenges include compatibility issues, system integration complexities, and optimizing communication efficiency.


Original Abstract Submitted

A protocol chip transmits the request from the host apparatus to a first processor through a first address translation unit. A first processor transmits a response to the request from the host apparatus, to the protocol chip through the first address translation unit. When the first processor stops processing, an instruction to transmit the request from the host apparatus to a second processor is transmitted to the protocol chip. When receiving the instruction to transmit the request from the host apparatus to the second processor, the protocol chip transmits the request from the host apparatus to the second processor through a second address translation unit. The second processor transmits the response to the request from the host apparatus to the protocol chip through the second address translation unit.