18215212. SEMICONDUCTOR PACKAGE simplified abstract (Samsung Electronics Co., Ltd.)

SEMICONDUCTOR PACKAGE

Organization Name

Samsung Electronics Co., Ltd.

Inventor(s)

Mina Choi of Suwon-si (KR)

Heejung Hwang of Suwon-si (KR)

SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18215212 titled 'SEMICONDUCTOR PACKAGE

The abstract describes a patent application for a package structure involving semiconductor chips, redistribution structures, encapsulants, and through-vias.

• The first package structure includes a first redistribution structure, at least one semiconductor chip, a first encapsulant, and a first through-via.
• The second package structure includes a second redistribution structure, at least one semiconductor chip, a second encapsulant, and a second through-via.
• The second package structure is placed on top of the first package structure.
• The through-vias pass through the encapsulants and are positioned between non-active surfaces.

Potential Applications: - This technology could be used in the semiconductor industry for advanced packaging solutions. - It may find applications in electronic devices where compact and efficient packaging is essential.

Problems Solved: - Provides a compact and efficient packaging solution for semiconductor chips. - Ensures proper connectivity and protection for the chips.

Benefits: - Improved packaging efficiency. - Enhanced protection for semiconductor chips. - Better connectivity between components.

Commercial Applications: Title: Advanced Semiconductor Packaging Technology for Enhanced Efficiency This technology could be commercially applied in the semiconductor industry for manufacturing advanced electronic devices with improved performance and reliability.

Questions about the technology: 1. How does this packaging technology compare to traditional methods? - This packaging technology offers improved efficiency and protection for semiconductor chips compared to traditional methods. 2. What are the potential cost implications of implementing this technology? - Implementing this technology may initially have higher costs but could lead to long-term savings through improved performance and reliability.

Original Abstract Submitted

A first package structure including a first redistribution structure, at least one first semiconductor chip disposed on the first redistribution structure, a first encapsulant covering the at least one first semiconductor chip, and a first through-via passing through the first encapsulant; a second package structure including a second redistribution structure, at least one second semiconductor chip disposed on the second redistribution structure, a second encapsulant covering the at least one second semiconductor chip, and a second through-via passing through the second encapsulant. The second package structure is disposed on the first package structure. At least one of a first upper end of the first through-via or a second upper end of the second through-via is between a first non-active surface and a second non-active surface.